Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24519561	1		T1	150		T2	143757		T3	176480
full_word	7628814	1		T1	3		T2	25656		T3	28406

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32148085	1		T1	153		T2	169413		T3	204886
auto[TlIntgErrCmd]	105	1		T97	3		T99	13		T215	9
auto[TlIntgErrData]	96	1		T97	3		T99	2		T215	5
auto[TlIntgErrBoth]	89	1		T97	4		T99	5		T215	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27689477	1		T1	145		T2	150524		T3	183054
auto[1]	4458898	1		T1	8		T2	18889		T3	21832

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23860795	1		T1	144		T2	141246		T3	173634
auto[TlIntgErrNone]	partial	auto[1]	658498	1		T1	6		T2	2511		T3	2846
auto[TlIntgErrNone]	full_word	auto[0]	3828544	1		T1	1		T2	9278		T3	9420
auto[TlIntgErrNone]	full_word	auto[1]	3800248	1		T1	2		T2	16378		T3	18986
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T97	2		T99	4		T215	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T97	1		T99	7		T215	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T99	1		T215	1		T219	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T99	1		T215	1		T219	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T215	3		T252	2		T218	2
auto[TlIntgErrData]	partial	auto[1]	43	1		T97	3		T99	2		T215	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T252	1		T218	1		T219	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T218	1		T335	1		T336	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T99	1		T215	4		T252	4
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T97	4		T99	3		T215	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T99	1		T218	1		T330	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19220	1		T64	32		T97	9		T99	18
full_word	4110446	1		T2	41220		T3	40992		T6	17029

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4129402	1		T2	41220		T3	40992		T6	17029
auto[TlIntgErrCmd]	93	1		T97	3		T99	8		T215	6
auto[TlIntgErrData]	93	1		T97	4		T99	6		T215	9
auto[TlIntgErrBoth]	78	1		T97	3		T99	5		T215	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4104945	1		T2	41220		T3	40992		T6	17029
auto[1]	24721	1		T64	35		T97	6		T99	12

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1231	1		T64	2		T202	45		T203	51
auto[TlIntgErrNone]	partial	auto[1]	17743	1		T64	30		T202	328		T203	911
auto[TlIntgErrNone]	full_word	auto[0]	4103598	1		T2	41220		T3	40992		T6	17029
auto[TlIntgErrNone]	full_word	auto[1]	6830	1		T64	5		T202	262		T203	423
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T97	1		T99	3		T215	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T97	2		T99	4		T215	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T219	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T99	1		T218	1		T219	1
auto[TlIntgErrData]	partial	auto[0]	50	1		T97	2		T99	3		T215	4
auto[TlIntgErrData]	partial	auto[1]	37	1		T97	1		T99	3		T215	5
auto[TlIntgErrData]	full_word	auto[0]	5	1		T97	1		T265	1		T331	2
auto[TlIntgErrData]	full_word	auto[1]	1	1		T337	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	21	1		T99	1		T215	2		T218	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T97	3		T99	4		T215	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T330	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T219	1		T338	1		T332	1