Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1596932008	1593488132	0	0
CheckNGreaterZero_A	4128	4128	0	0
GntImpliesReady_A	1596932008	401237934	0	0
GntImpliesValid_A	1596932008	401237934	0	0
GrantKnown_A	1596932008	1593488132	0	0
IdxKnown_A	1596932008	1593488132	0	0
IndexIsCorrect_A	1596932008	401237934	0	0
NoReadyValidNoGrant_A	1596932008	174623618	0	0
Priority_A	1596932008	425656916	0	0
ReadyAndValidImplyGrant_A	1596932008	401237934	0	0
ReqAndReadyImplyGrant_A	1596932008	401237934	0	0
ReqImpliesValid_A	1596932008	425656916	0	0
ValidKnown_A	1596932008	1593488132	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	1593488132	0	0
T1	15168	12244	0	0
T2	1442780	1442488	0	0
T3	1670476	1670236	0	0
T4	8216	7964	0	0
T5	24944	22996	0	0
T6	316644	316152	0	0
T19	5692	5396	0	0
T20	13844	11044	0	0
T21	264268	263872	0	0
T22	4452	4208	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4128	4128	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0
T22	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	401237934	0	0
T1	7584	440	0	0
T2	1442780	474574	0	0
T3	1670476	549030	0	0
T4	8216	736	0	0
T5	24944	1384	0	0
T6	316644	52364	0	0
T19	5692	64	0	0
T20	13844	428	0	0
T21	264268	42776	0	0
T22	4452	64	0	0
T24	0	1134036	0	0
T26	1880	0	0	0
T39	0	32324	0	0
T54	0	14	0	0
T55	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	401237934	0	0
T1	7584	440	0	0
T2	1442780	474574	0	0
T3	1670476	549030	0	0
T4	8216	736	0	0
T5	24944	1384	0	0
T6	316644	52364	0	0
T19	5692	64	0	0
T20	13844	428	0	0
T21	264268	42776	0	0
T22	4452	64	0	0
T24	0	1134036	0	0
T26	1880	0	0	0
T39	0	32324	0	0
T54	0	14	0	0
T55	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	1593488132	0	0
T1	15168	12244	0	0
T2	1442780	1442488	0	0
T3	1670476	1670236	0	0
T4	8216	7964	0	0
T5	24944	22996	0	0
T6	316644	316152	0	0
T19	5692	5396	0	0
T20	13844	11044	0	0
T21	264268	263872	0	0
T22	4452	4208	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	1593488132	0	0
T1	15168	12244	0	0
T2	1442780	1442488	0	0
T3	1670476	1670236	0	0
T4	8216	7964	0	0
T5	24944	22996	0	0
T6	316644	316152	0	0
T19	5692	5396	0	0
T20	13844	11044	0	0
T21	264268	263872	0	0
T22	4452	4208	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	401237934	0	0
T1	7584	440	0	0
T2	1442780	474574	0	0
T3	1670476	549030	0	0
T4	8216	736	0	0
T5	24944	1384	0	0
T6	316644	52364	0	0
T19	5692	64	0	0
T20	13844	428	0	0
T21	264268	42776	0	0
T22	4452	64	0	0
T24	0	1134036	0	0
T26	1880	0	0	0
T39	0	32324	0	0
T54	0	14	0	0
T55	0	18	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	174623618	0	0
T1	7584	1664	0	0
T2	1442780	311302	0	0
T3	1670476	192114	0	0
T4	8216	302	0	0
T5	24944	3292	0	0
T6	316644	150492	0	0
T19	5692	256	0	0
T20	13844	1564	0	0
T21	264268	124206	0	0
T22	4452	256	0	0
T24	0	7998	0	0
T26	1880	0	0	0
T39	0	926	0	0
T54	0	38	0	0
T55	0	28	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	425656916	0	0
T1	7584	440	0	0
T2	1442780	520636	0	0
T3	1670476	678794	0	0
T4	8216	736	0	0
T5	24944	1384	0	0
T6	316644	55700	0	0
T19	5692	64	0	0
T20	13844	428	0	0
T21	264268	45816	0	0
T22	4452	64	0	0
T24	0	1134036	0	0
T26	1880	0	0	0
T39	0	32348	0	0
T54	0	14	0	0
T55	0	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	401237934	0	0
T1	7584	440	0	0
T2	1442780	474574	0	0
T3	1670476	549030	0	0
T4	8216	736	0	0
T5	24944	1384	0	0
T6	316644	52364	0	0
T19	5692	64	0	0
T20	13844	428	0	0
T21	264268	42776	0	0
T22	4452	64	0	0
T24	0	1134036	0	0
T26	1880	0	0	0
T39	0	32324	0	0
T54	0	14	0	0
T55	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	401237934	0	0
T1	7584	440	0	0
T2	1442780	474574	0	0
T3	1670476	549030	0	0
T4	8216	736	0	0
T5	24944	1384	0	0
T6	316644	52364	0	0
T19	5692	64	0	0
T20	13844	428	0	0
T21	264268	42776	0	0
T22	4452	64	0	0
T24	0	1134036	0	0
T26	1880	0	0	0
T39	0	32324	0	0
T54	0	14	0	0
T55	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	425656916	0	0
T1	7584	440	0	0
T2	1442780	520636	0	0
T3	1670476	678794	0	0
T4	8216	736	0	0
T5	24944	1384	0	0
T6	316644	55700	0	0
T19	5692	64	0	0
T20	13844	428	0	0
T21	264268	45816	0	0
T22	4452	64	0	0
T24	0	1134036	0	0
T26	1880	0	0	0
T39	0	32348	0	0
T54	0	14	0	0
T55	0	18	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596932008	1593488132	0	0
T1	15168	12244	0	0
T2	1442780	1442488	0	0
T3	1670476	1670236	0	0
T4	8216	7964	0	0
T5	24944	22996	0	0
T6	316644	316152	0	0
T19	5692	5396	0	0
T20	13844	11044	0	0
T21	264268	263872	0	0
T22	4452	4208	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399233002	398372033	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	399233002	111415903	0	0
GntImpliesValid_A	399233002	111415903	0	0
GrantKnown_A	399233002	398372033	0	0
IdxKnown_A	399233002	398372033	0	0
IndexIsCorrect_A	399233002	111415903	0	0
NoReadyValidNoGrant_A	399233002	46538066	0	0
Priority_A	399233002	117540832	0	0
ReadyAndValidImplyGrant_A	399233002	111415903	0	0
ReqAndReadyImplyGrant_A	399233002	111415903	0	0
ReqImpliesValid_A	399233002	117540832	0	0
ValidKnown_A	399233002	398372033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	111415903	0	0
T1	3792	220	0	0
T2	360695	110264	0	0
T3	417619	178382	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18241	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12180	0	0
T22	1113	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	111415903	0	0
T1	3792	220	0	0
T2	360695	110264	0	0
T3	417619	178382	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18241	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12180	0	0
T22	1113	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	111415903	0	0
T1	3792	220	0	0
T2	360695	110264	0	0
T3	417619	178382	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18241	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12180	0	0
T22	1113	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	46538066	0	0
T1	3792	832	0	0
T2	360695	78662	0	0
T3	417619	56863	0	0
T4	2054	128	0	0
T5	6236	1293	0	0
T6	79161	50036	0	0
T19	1423	128	0	0
T20	3461	782	0	0
T21	66067	34560	0	0
T22	1113	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	117540832	0	0
T1	3792	220	0	0
T2	360695	123697	0	0
T3	417619	215313	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18694	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12709	0	0
T22	1113	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	111415903	0	0
T1	3792	220	0	0
T2	360695	110264	0	0
T3	417619	178382	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18241	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12180	0	0
T22	1113	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	111415903	0	0
T1	3792	220	0	0
T2	360695	110264	0	0
T3	417619	178382	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18241	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12180	0	0
T22	1113	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	117540832	0	0
T1	3792	220	0	0
T2	360695	123697	0	0
T3	417619	215313	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18694	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12709	0	0
T22	1113	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399233002	398372033	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	399233002	111415947	0	0
GntImpliesValid_A	399233002	111415947	0	0
GrantKnown_A	399233002	398372033	0	0
IdxKnown_A	399233002	398372033	0	0
IndexIsCorrect_A	399233002	111415947	0	0
NoReadyValidNoGrant_A	399233002	46537972	0	0
Priority_A	399233002	117540970	0	0
ReadyAndValidImplyGrant_A	399233002	111415947	0	0
ReqAndReadyImplyGrant_A	399233002	111415947	0	0
ReqImpliesValid_A	399233002	117540970	0	0
ValidKnown_A	399233002	398372033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	111415947	0	0
T1	3792	220	0	0
T2	360695	110264	0	0
T3	417619	178382	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18241	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12180	0	0
T22	1113	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	111415947	0	0
T1	3792	220	0	0
T2	360695	110264	0	0
T3	417619	178382	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18241	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12180	0	0
T22	1113	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	111415947	0	0
T1	3792	220	0	0
T2	360695	110264	0	0
T3	417619	178382	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18241	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12180	0	0
T22	1113	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	46537972	0	0
T1	3792	832	0	0
T2	360695	78662	0	0
T3	417619	56863	0	0
T4	2054	128	0	0
T5	6236	1293	0	0
T6	79161	50036	0	0
T19	1423	128	0	0
T20	3461	782	0	0
T21	66067	34560	0	0
T22	1113	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	117540970	0	0
T1	3792	220	0	0
T2	360695	123697	0	0
T3	417619	215313	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18694	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12709	0	0
T22	1113	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	111415947	0	0
T1	3792	220	0	0
T2	360695	110264	0	0
T3	417619	178382	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18241	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12180	0	0
T22	1113	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	111415947	0	0
T1	3792	220	0	0
T2	360695	110264	0	0
T3	417619	178382	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18241	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12180	0	0
T22	1113	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	117540970	0	0
T1	3792	220	0	0
T2	360695	123697	0	0
T3	417619	215313	0	0
T4	2054	353	0	0
T5	6236	492	0	0
T6	79161	18694	0	0
T19	1423	32	0	0
T20	3461	214	0	0
T21	66067	12709	0	0
T22	1113	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399233002	398372033	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	399233002	89203087	0	0
GntImpliesValid_A	399233002	89203087	0	0
GrantKnown_A	399233002	398372033	0	0
IdxKnown_A	399233002	398372033	0	0
IndexIsCorrect_A	399233002	89203087	0	0
NoReadyValidNoGrant_A	399233002	40773790	0	0
Priority_A	399233002	95287602	0	0
ReadyAndValidImplyGrant_A	399233002	89203087	0	0
ReqAndReadyImplyGrant_A	399233002	89203087	0	0
ReqImpliesValid_A	399233002	95287602	0	0
ValidKnown_A	399233002	398372033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	89203087	0	0
T2	360695	127023	0	0
T3	417619	96133	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	7941	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	9208	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16162	0	0
T54	0	7	0	0
T55	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	89203087	0	0
T2	360695	127023	0	0
T3	417619	96133	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	7941	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	9208	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16162	0	0
T54	0	7	0	0
T55	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	89203087	0	0
T2	360695	127023	0	0
T3	417619	96133	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	7941	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	9208	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16162	0	0
T54	0	7	0	0
T55	0	9	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	40773790	0	0
T2	360695	76989	0	0
T3	417619	39194	0	0
T4	2054	23	0	0
T5	6236	353	0	0
T6	79161	25210	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	27543	0	0
T22	1113	0	0	0
T24	0	3999	0	0
T26	940	0	0	0
T39	0	463	0	0
T54	0	19	0	0
T55	0	14	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	95287602	0	0
T2	360695	136621	0	0
T3	417619	124084	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	9156	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	10199	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16174	0	0
T54	0	7	0	0
T55	0	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	89203087	0	0
T2	360695	127023	0	0
T3	417619	96133	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	7941	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	9208	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16162	0	0
T54	0	7	0	0
T55	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	89203087	0	0
T2	360695	127023	0	0
T3	417619	96133	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	7941	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	9208	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16162	0	0
T54	0	7	0	0
T55	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	95287602	0	0
T2	360695	136621	0	0
T3	417619	124084	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	9156	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	10199	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16174	0	0
T54	0	7	0	0
T55	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399233002	398372033	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	399233002	89202997	0	0
GntImpliesValid_A	399233002	89202997	0	0
GrantKnown_A	399233002	398372033	0	0
IdxKnown_A	399233002	398372033	0	0
IndexIsCorrect_A	399233002	89202997	0	0
NoReadyValidNoGrant_A	399233002	40773790	0	0
Priority_A	399233002	95287512	0	0
ReadyAndValidImplyGrant_A	399233002	89202997	0	0
ReqAndReadyImplyGrant_A	399233002	89202997	0	0
ReqImpliesValid_A	399233002	95287512	0	0
ValidKnown_A	399233002	398372033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	89202997	0	0
T2	360695	127023	0	0
T3	417619	96133	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	7941	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	9208	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16162	0	0
T54	0	7	0	0
T55	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	89202997	0	0
T2	360695	127023	0	0
T3	417619	96133	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	7941	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	9208	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16162	0	0
T54	0	7	0	0
T55	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	89202997	0	0
T2	360695	127023	0	0
T3	417619	96133	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	7941	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	9208	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16162	0	0
T54	0	7	0	0
T55	0	9	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	40773790	0	0
T2	360695	76989	0	0
T3	417619	39194	0	0
T4	2054	23	0	0
T5	6236	353	0	0
T6	79161	25210	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	27543	0	0
T22	1113	0	0	0
T24	0	3999	0	0
T26	940	0	0	0
T39	0	463	0	0
T54	0	19	0	0
T55	0	14	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	95287512	0	0
T2	360695	136621	0	0
T3	417619	124084	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	9156	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	10199	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16174	0	0
T54	0	7	0	0
T55	0	9	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	89202997	0	0
T2	360695	127023	0	0
T3	417619	96133	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	7941	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	9208	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16162	0	0
T54	0	7	0	0
T55	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	89202997	0	0
T2	360695	127023	0	0
T3	417619	96133	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	7941	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	9208	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16162	0	0
T54	0	7	0	0
T55	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	95287512	0	0
T2	360695	136621	0	0
T3	417619	124084	0	0
T4	2054	15	0	0
T5	6236	200	0	0
T6	79161	9156	0	0
T19	1423	0	0	0
T20	3461	0	0	0
T21	66067	10199	0	0
T22	1113	0	0	0
T24	0	567018	0	0
T26	940	0	0	0
T39	0	16174	0	0
T54	0	7	0	0
T55	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399233002	398372033	0	0
T1	3792	3061	0	0
T2	360695	360622	0	0
T3	417619	417559	0	0
T4	2054	1991	0	0
T5	6236	5749	0	0
T6	79161	79038	0	0
T19	1423	1349	0	0
T20	3461	2761	0	0
T21	66067	65968	0	0
T22	1113	1052	0	0