Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	401690832	4032	0	0
addr_rd_A	401690832	1798	0	0
bank0_info0_page_cfg_0_rd_A	401690832	3014	0	0
bank0_info0_page_cfg_1_rd_A	401690832	2174	0	0
bank0_info0_page_cfg_2_rd_A	401690832	2494	0	0
bank0_info0_page_cfg_3_rd_A	401690832	3170	0	0
bank0_info0_page_cfg_4_rd_A	401690832	2817	0	0
bank0_info0_page_cfg_5_rd_A	401690832	2903	0	0
bank0_info0_page_cfg_6_rd_A	401690832	3152	0	0
bank0_info0_page_cfg_7_rd_A	401690832	3063	0	0
bank0_info0_page_cfg_8_rd_A	401690832	2510	0	0
bank0_info0_page_cfg_9_rd_A	401690832	3211	0	0
bank0_info0_regwen_0_rd_A	401690832	2212	0	0
bank0_info0_regwen_1_rd_A	401690832	2259	0	0
bank0_info0_regwen_2_rd_A	401690832	2361	0	0
bank0_info0_regwen_3_rd_A	401690832	2225	0	0
bank0_info0_regwen_4_rd_A	401690832	748	0	0
bank0_info0_regwen_5_rd_A	401690832	2308	0	0
bank0_info0_regwen_6_rd_A	401690832	2257	0	0
bank0_info0_regwen_7_rd_A	401690832	1242	0	0
bank0_info0_regwen_8_rd_A	401690832	1757	0	0
bank0_info0_regwen_9_rd_A	401690832	1753	0	0
bank0_info1_page_cfg_rd_A	401690832	2973	0	0
bank0_info1_regwen_rd_A	401690832	2326	0	0
bank0_info2_page_cfg_0_rd_A	401690832	2625	0	0
bank0_info2_page_cfg_1_rd_A	401690832	3071	0	0
bank0_info2_regwen_0_rd_A	401690832	1886	0	0
bank0_info2_regwen_1_rd_A	401690832	2155	0	0
bank1_info0_page_cfg_0_rd_A	401690832	2468	0	0
bank1_info0_page_cfg_1_rd_A	401690832	2251	0	0
bank1_info0_page_cfg_2_rd_A	401690832	3166	0	0
bank1_info0_page_cfg_3_rd_A	401690832	2613	0	0
bank1_info0_page_cfg_4_rd_A	401690832	2355	0	0
bank1_info0_page_cfg_5_rd_A	401690832	2772	0	0
bank1_info0_page_cfg_6_rd_A	401690832	2647	0	0
bank1_info0_page_cfg_7_rd_A	401690832	2080	0	0
bank1_info0_page_cfg_8_rd_A	401690832	2686	0	0
bank1_info0_page_cfg_9_rd_A	401690832	2542	0	0
bank1_info0_regwen_0_rd_A	401690832	1564	0	0
bank1_info0_regwen_1_rd_A	401690832	2268	0	0
bank1_info0_regwen_2_rd_A	401690832	1715	0	0
bank1_info0_regwen_3_rd_A	401690832	2413	0	0
bank1_info0_regwen_4_rd_A	401690832	2311	0	0
bank1_info0_regwen_5_rd_A	401690832	2196	0	0
bank1_info0_regwen_6_rd_A	401690832	2244	0	0
bank1_info0_regwen_7_rd_A	401690832	756	0	0
bank1_info0_regwen_8_rd_A	401690832	1212	0	0
bank1_info0_regwen_9_rd_A	401690832	2217	0	0
bank1_info1_page_cfg_rd_A	401690832	3266	0	0
bank1_info1_regwen_rd_A	401690832	2254	0	0
bank1_info2_page_cfg_0_rd_A	401690832	2970	0	0
bank1_info2_page_cfg_1_rd_A	401690832	2680	0	0
bank1_info2_regwen_0_rd_A	401690832	1767	0	0
bank1_info2_regwen_1_rd_A	401690832	2215	0	0
bank_cfg_regwen_rd_A	401690832	1353	0	0
default_region_rd_A	401690832	2416	0	0
exec_rd_A	401690832	2240	0	0
fifo_lvl_rd_A	401690832	1450	0	0
fifo_rst_rd_A	401690832	2207	0	0
hw_info_cfg_override_rd_A	401690832	1889	0	0
intr_enable_rd_A	401690832	2420	0	0
mp_region_0_rd_A	401690832	1800	0	0
mp_region_1_rd_A	401690832	2392	0	0
mp_region_2_rd_A	401690832	2328	0	0
mp_region_3_rd_A	401690832	1431	0	0
mp_region_4_rd_A	401690832	2488	0	0
mp_region_5_rd_A	401690832	2222	0	0
mp_region_6_rd_A	401690832	2515	0	0
mp_region_7_rd_A	401690832	2336	0	0
mp_region_cfg_0_rd_A	401690832	2768	0	0
mp_region_cfg_1_rd_A	401690832	2804	0	0
mp_region_cfg_2_rd_A	401690832	1963	0	0
mp_region_cfg_3_rd_A	401690832	2822	0	0
mp_region_cfg_4_rd_A	401690832	2702	0	0
mp_region_cfg_5_rd_A	401690832	2659	0	0
mp_region_cfg_6_rd_A	401690832	2556	0	0
mp_region_cfg_7_rd_A	401690832	2692	0	0
phy_alert_cfg_rd_A	401690832	1243	0	0
region_cfg_regwen_0_rd_A	401690832	1836	0	0
region_cfg_regwen_1_rd_A	401690832	1601	0	0
region_cfg_regwen_2_rd_A	401690832	1715	0	0
region_cfg_regwen_3_rd_A	401690832	2227	0	0
region_cfg_regwen_4_rd_A	401690832	1323	0	0
region_cfg_regwen_5_rd_A	401690832	1685	0	0
region_cfg_regwen_6_rd_A	401690832	2181	0	0
region_cfg_regwen_7_rd_A	401690832	2124	0	0
scratch_rd_A	401690832	1764	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	4032	0	0
T64	5194	5	0	0
T97	41817	3	0	0
T99	96608	2	0	0
T202	3715	22	0	0
T203	5393	279	0	0
T204	4564	52	0	0
T215	34076	2	0	0
T216	8974	5	0	0
T217	3015	39	0	0
T252	33822	1	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1798	0	0
T97	41817	43	0	0
T99	96608	6	0	0
T216	8974	9	0	0
T259	2405	3	0	0
T278	7289	8	0	0
T279	9140	28	0	0
T280	5362	10	0	0
T281	7261	8	0	0
T282	18130	36	0	0
T283	5715	12	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	3014	0	0
T63	10197	26	0	0
T64	5194	3	0	0
T97	41817	101	0	0
T99	96608	171	0	0
T216	8974	9	0	0
T278	7289	10	0	0
T279	9140	21	0	0
T280	5362	6	0	0
T281	7261	60	0	0
T282	18130	16	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2174	0	0
T63	10197	53	0	0
T64	5194	3	0	0
T97	41817	124	0	0
T99	96608	246	0	0
T216	8974	31	0	0
T278	7289	67	0	0
T279	9140	18	0	0
T280	5362	43	0	0
T281	7261	4	0	0
T282	18130	23	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2494	0	0
T63	10197	35	0	0
T64	5194	12	0	0
T97	41817	104	0	0
T99	96608	122	0	0
T216	8974	23	0	0
T259	2405	5	0	0
T278	7289	66	0	0
T279	9140	10	0	0
T280	5362	11	0	0
T281	7261	50	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	3170	0	0
T63	10197	12	0	0
T64	5194	21	0	0
T97	41817	124	0	0
T99	96608	226	0	0
T216	8974	26	0	0
T259	2405	6	0	0
T278	7289	28	0	0
T280	5362	7	0	0
T281	7261	19	0	0
T282	18130	9	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2817	0	0
T63	10197	23	0	0
T64	5194	10	0	0
T97	41817	100	0	0
T99	96608	198	0	0
T216	8974	8	0	0
T278	7289	19	0	0
T281	7261	57	0	0
T282	18130	18	0	0
T283	5715	18	0	0
T284	10348	52	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2903	0	0
T63	10197	7	0	0
T64	5194	14	0	0
T97	41817	236	0	0
T99	96608	175	0	0
T216	8974	26	0	0
T278	7289	47	0	0
T279	9140	18	0	0
T280	5362	10	0	0
T281	7261	72	0	0
T282	18130	85	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	3152	0	0
T63	10197	12	0	0
T64	5194	4	0	0
T97	41817	164	0	0
T99	96608	201	0	0
T216	8974	18	0	0
T278	7289	8	0	0
T279	9140	10	0	0
T280	5362	45	0	0
T281	7261	20	0	0
T282	18130	47	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	3063	0	0
T63	10197	61	0	0
T64	5194	9	0	0
T97	41817	235	0	0
T99	96608	168	0	0
T216	8974	13	0	0
T278	7289	9	0	0
T279	9140	8	0	0
T280	5362	40	0	0
T281	7261	29	0	0
T282	18130	32	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2510	0	0
T63	10197	32	0	0
T64	5194	6	0	0
T97	41817	142	0	0
T99	96608	168	0	0
T216	8974	16	0	0
T259	2405	5	0	0
T278	7289	32	0	0
T280	5362	9	0	0
T281	7261	4	0	0
T282	18130	17	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	3211	0	0
T63	10197	25	0	0
T64	5194	1	0	0
T97	41817	151	0	0
T99	96608	194	0	0
T216	8974	66	0	0
T278	7289	29	0	0
T279	9140	5	0	0
T280	5362	4	0	0
T281	7261	8	0	0
T282	18130	34	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2212	0	0
T63	10197	17	0	0
T64	5194	8	0	0
T97	41817	56	0	0
T99	96608	47	0	0
T216	8974	8	0	0
T278	7289	9	0	0
T279	9140	4	0	0
T280	5362	13	0	0
T281	7261	6	0	0
T282	18130	37	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2259	0	0
T63	10197	7	0	0
T97	41817	31	0	0
T99	96608	51	0	0
T216	8974	1	0	0
T259	2405	1	0	0
T278	7289	1	0	0
T279	9140	9	0	0
T280	5362	7	0	0
T281	7261	10	0	0
T282	18130	56	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2361	0	0
T63	10197	38	0	0
T64	5194	1	0	0
T97	41817	23	0	0
T99	96608	47	0	0
T216	8974	7	0	0
T278	7289	8	0	0
T279	9140	6	0	0
T280	5362	12	0	0
T281	7261	6	0	0
T282	18130	68	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2225	0	0
T63	10197	3	0	0
T64	5194	9	0	0
T97	41817	31	0	0
T99	96608	37	0	0
T216	8974	7	0	0
T278	7289	6	0	0
T279	9140	5	0	0
T280	5362	13	0	0
T281	7261	5	0	0
T282	18130	53	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	748	0	0
T64	5194	8	0	0
T97	41817	48	0	0
T99	96608	44	0	0
T216	8974	4	0	0
T278	7289	18	0	0
T279	9140	17	0	0
T280	5362	5	0	0
T281	7261	6	0	0
T282	18130	48	0	0
T283	5715	4	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2308	0	0
T63	10197	36	0	0
T64	5194	1	0	0
T97	41817	33	0	0
T99	96608	43	0	0
T216	8974	11	0	0
T278	7289	6	0	0
T279	9140	44	0	0
T280	5362	1	0	0
T281	7261	1	0	0
T282	18130	98	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2257	0	0
T63	10197	22	0	0
T64	5194	5	0	0
T97	41817	40	0	0
T99	96608	50	0	0
T259	2405	9	0	0
T278	7289	8	0	0
T279	9140	31	0	0
T280	5362	5	0	0
T281	7261	7	0	0
T282	18130	23	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1242	0	0
T63	10197	29	0	0
T97	41817	43	0	0
T99	96608	30	0	0
T216	8974	26	0	0
T259	2405	6	0	0
T278	7289	5	0	0
T279	9140	24	0	0
T280	5362	10	0	0
T281	7261	14	0	0
T282	18130	32	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1757	0	0
T63	10197	18	0	0
T64	5194	2	0	0
T97	41817	32	0	0
T99	96608	52	0	0
T216	8974	15	0	0
T259	2405	4	0	0
T278	7289	9	0	0
T279	9140	4	0	0
T280	5362	1	0	0
T281	7261	1	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1753	0	0
T63	10197	25	0	0
T64	5194	1	0	0
T97	41817	44	0	0
T99	96608	53	0	0
T278	7289	4	0	0
T279	9140	10	0	0
T280	5362	10	0	0
T281	7261	8	0	0
T282	18130	30	0	0
T283	5715	6	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2973	0	0
T63	10197	7	0	0
T64	5194	1	0	0
T97	41817	141	0	0
T99	96608	162	0	0
T278	7289	42	0	0
T279	9140	20	0	0
T280	5362	32	0	0
T281	7261	66	0	0
T282	18130	2	0	0
T283	5715	35	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2326	0	0
T63	10197	46	0	0
T64	5194	5	0	0
T97	41817	38	0	0
T99	96608	43	0	0
T216	8974	6	0	0
T278	7289	6	0	0
T279	9140	19	0	0
T280	5362	7	0	0
T281	7261	10	0	0
T282	18130	19	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2625	0	0
T63	10197	52	0	0
T97	41817	154	0	0
T99	96608	161	0	0
T216	8974	21	0	0
T259	2405	9	0	0
T278	7289	21	0	0
T280	5362	14	0	0
T281	7261	35	0	0
T282	18130	32	0	0
T283	5715	3	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	3071	0	0
T63	10197	2	0	0
T64	5194	15	0	0
T97	41817	177	0	0
T99	96608	218	0	0
T216	8974	19	0	0
T259	2405	2	0	0
T278	7289	52	0	0
T279	9140	9	0	0
T280	5362	19	0	0
T281	7261	33	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1886	0	0
T63	10197	40	0	0
T64	5194	14	0	0
T97	41817	36	0	0
T99	96608	34	0	0
T216	8974	21	0	0
T259	2405	2	0	0
T278	7289	7	0	0
T279	9140	18	0	0
T280	5362	7	0	0
T281	7261	8	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2155	0	0
T63	10197	29	0	0
T97	41817	37	0	0
T99	96608	33	0	0
T216	8974	10	0	0
T259	2405	4	0	0
T278	7289	11	0	0
T279	9140	1	0	0
T280	5362	9	0	0
T281	7261	8	0	0
T282	18130	48	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2468	0	0
T63	10197	4	0	0
T64	5194	22	0	0
T97	41817	131	0	0
T99	96608	211	0	0
T216	8974	25	0	0
T259	2405	2	0	0
T278	7289	30	0	0
T279	9140	2	0	0
T280	5362	13	0	0
T281	7261	39	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2251	0	0
T63	10197	16	0	0
T64	5194	18	0	0
T97	41817	210	0	0
T99	96608	174	0	0
T216	8974	5	0	0
T259	2405	7	0	0
T278	7289	64	0	0
T279	9140	10	0	0
T280	5362	3	0	0
T281	7261	25	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	3166	0	0
T63	10197	51	0	0
T64	5194	20	0	0
T97	41817	206	0	0
T99	96608	140	0	0
T216	8974	44	0	0
T259	2405	7	0	0
T278	7289	44	0	0
T279	9140	9	0	0
T280	5362	28	0	0
T281	7261	28	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2613	0	0
T63	10197	12	0	0
T64	5194	4	0	0
T97	41817	229	0	0
T99	96608	172	0	0
T216	8974	35	0	0
T278	7289	25	0	0
T279	9140	9	0	0
T280	5362	28	0	0
T281	7261	52	0	0
T282	18130	16	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2355	0	0
T63	10197	58	0	0
T64	5194	9	0	0
T97	41817	167	0	0
T99	96608	225	0	0
T216	8974	31	0	0
T259	2405	3	0	0
T278	7289	28	0	0
T279	9140	6	0	0
T280	5362	31	0	0
T281	7261	57	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2772	0	0
T63	10197	18	0	0
T64	5194	18	0	0
T97	41817	177	0	0
T99	96608	150	0	0
T216	8974	12	0	0
T259	2405	3	0	0
T278	7289	2	0	0
T279	9140	8	0	0
T280	5362	13	0	0
T281	7261	6	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2647	0	0
T63	10197	47	0	0
T64	5194	20	0	0
T97	41817	186	0	0
T99	96608	137	0	0
T216	8974	19	0	0
T259	2405	9	0	0
T278	7289	49	0	0
T280	5362	23	0	0
T281	7261	11	0	0
T282	18130	49	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2080	0	0
T97	41817	165	0	0
T99	96608	231	0	0
T216	8974	2	0	0
T259	2405	9	0	0
T278	7289	51	0	0
T280	5362	7	0	0
T281	7261	62	0	0
T282	18130	84	0	0
T283	5715	8	0	0
T284	10348	57	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2686	0	0
T63	10197	53	0	0
T64	5194	27	0	0
T97	41817	196	0	0
T99	96608	179	0	0
T216	8974	36	0	0
T259	2405	1	0	0
T278	7289	29	0	0
T279	9140	17	0	0
T280	5362	18	0	0
T281	7261	40	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2542	0	0
T63	10197	23	0	0
T64	5194	15	0	0
T97	41817	177	0	0
T99	96608	170	0	0
T216	8974	5	0	0
T259	2405	7	0	0
T278	7289	10	0	0
T279	9140	5	0	0
T280	5362	3	0	0
T281	7261	62	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1564	0	0
T63	10197	15	0	0
T64	5194	4	0	0
T97	41817	29	0	0
T99	96608	22	0	0
T216	8974	9	0	0
T278	7289	3	0	0
T279	9140	11	0	0
T280	5362	1	0	0
T281	7261	9	0	0
T282	18130	43	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2268	0	0
T63	10197	32	0	0
T64	5194	1	0	0
T97	41817	19	0	0
T99	96608	75	0	0
T216	8974	7	0	0
T278	7289	2	0	0
T279	9140	15	0	0
T280	5362	1	0	0
T281	7261	2	0	0
T282	18130	62	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1715	0	0
T63	10197	18	0	0
T97	41817	37	0	0
T99	96608	41	0	0
T216	8974	6	0	0
T259	2405	5	0	0
T278	7289	9	0	0
T279	9140	10	0	0
T280	5362	6	0	0
T281	7261	14	0	0
T282	18130	30	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2413	0	0
T63	10197	45	0	0
T64	5194	12	0	0
T97	41817	32	0	0
T99	96608	44	0	0
T216	8974	19	0	0
T259	2405	6	0	0
T279	9140	22	0	0
T280	5362	9	0	0
T281	7261	3	0	0
T282	18130	80	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2311	0	0
T63	10197	23	0	0
T97	41817	45	0	0
T99	96608	47	0	0
T216	8974	6	0	0
T278	7289	4	0	0
T279	9140	4	0	0
T280	5362	1	0	0
T281	7261	8	0	0
T282	18130	64	0	0
T283	5715	7	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2196	0	0
T63	10197	29	0	0
T97	41817	29	0	0
T99	96608	70	0	0
T216	8974	14	0	0
T259	2405	5	0	0
T278	7289	6	0	0
T279	9140	26	0	0
T280	5362	9	0	0
T281	7261	2	0	0
T282	18130	22	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2244	0	0
T63	10197	23	0	0
T64	5194	3	0	0
T97	41817	43	0	0
T99	96608	50	0	0
T216	8974	11	0	0
T259	2405	7	0	0
T278	7289	4	0	0
T279	9140	23	0	0
T280	5362	2	0	0
T281	7261	13	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	756	0	0
T64	5194	3	0	0
T97	41817	38	0	0
T99	96608	31	0	0
T259	2405	9	0	0
T278	7289	5	0	0
T279	9140	21	0	0
T280	5362	5	0	0
T281	7261	13	0	0
T282	18130	86	0	0
T283	5715	2	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1212	0	0
T63	10197	36	0	0
T97	41817	33	0	0
T99	96608	47	0	0
T216	8974	7	0	0
T259	2405	2	0	0
T278	7289	4	0	0
T279	9140	16	0	0
T280	5362	11	0	0
T281	7261	4	0	0
T282	18130	47	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2217	0	0
T63	10197	11	0	0
T64	5194	4	0	0
T97	41817	40	0	0
T99	96608	46	0	0
T216	8974	14	0	0
T278	7289	6	0	0
T279	9140	12	0	0
T280	5362	9	0	0
T281	7261	6	0	0
T282	18130	42	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	3266	0	0
T63	10197	53	0	0
T64	5194	8	0	0
T97	41817	138	0	0
T99	96608	201	0	0
T216	8974	43	0	0
T278	7289	31	0	0
T279	9140	3	0	0
T280	5362	16	0	0
T281	7261	64	0	0
T282	18130	28	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2254	0	0
T63	10197	30	0	0
T64	5194	4	0	0
T97	41817	61	0	0
T99	96608	42	0	0
T216	8974	8	0	0
T278	7289	10	0	0
T279	9140	4	0	0
T280	5362	8	0	0
T281	7261	8	0	0
T282	18130	76	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2970	0	0
T63	10197	1	0	0
T64	5194	17	0	0
T97	41817	136	0	0
T99	96608	186	0	0
T216	8974	29	0	0
T278	7289	31	0	0
T279	9140	21	0	0
T280	5362	35	0	0
T281	7261	49	0	0
T282	18130	48	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2680	0	0
T63	10197	34	0	0
T64	5194	21	0	0
T97	41817	156	0	0
T99	96608	139	0	0
T216	8974	11	0	0
T278	7289	10	0	0
T279	9140	22	0	0
T280	5362	32	0	0
T281	7261	10	0	0
T282	18130	22	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1767	0	0
T63	10197	5	0	0
T64	5194	1	0	0
T97	41817	48	0	0
T99	96608	51	0	0
T216	8974	8	0	0
T259	2405	2	0	0
T278	7289	4	0	0
T279	9140	11	0	0
T280	5362	10	0	0
T281	7261	18	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2215	0	0
T63	10197	29	0	0
T64	5194	5	0	0
T97	41817	48	0	0
T99	96608	51	0	0
T216	8974	5	0	0
T278	7289	11	0	0
T279	9140	2	0	0
T281	7261	11	0	0
T282	18130	84	0	0
T283	5715	11	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1353	0	0
T63	10197	19	0	0
T64	5194	6	0	0
T97	41817	39	0	0
T99	96608	25	0	0
T216	8974	13	0	0
T278	7289	6	0	0
T279	9140	20	0	0
T280	5362	6	0	0
T281	7261	8	0	0
T282	18130	79	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2416	0	0
T63	10197	20	0	0
T64	5194	10	0	0
T97	41817	130	0	0
T99	96608	138	0	0
T216	8974	15	0	0
T259	2405	4	0	0
T278	7289	37	0	0
T279	9140	14	0	0
T280	5362	37	0	0
T281	7261	62	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2240	0	0
T63	10197	13	0	0
T64	5194	13	0	0
T97	41817	52	0	0
T99	96608	39	0	0
T216	8974	5	0	0
T259	2405	2	0	0
T278	7289	10	0	0
T279	9140	24	0	0
T280	5362	5	0	0
T281	7261	5	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1450	0	0
T63	10197	42	0	0
T64	5194	8	0	0
T97	41817	70	0	0
T99	96608	77	0	0
T216	8974	10	0	0
T259	2405	3	0	0
T278	7289	17	0	0
T279	9140	12	0	0
T280	5362	2	0	0
T281	7261	8	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2207	0	0
T63	10197	19	0	0
T64	5194	7	0	0
T97	41817	34	0	0
T99	96608	46	0	0
T216	8974	12	0	0
T259	2405	2	0	0
T278	7289	7	0	0
T279	9140	5	0	0
T280	5362	15	0	0
T281	7261	8	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1889	0	0
T63	10197	17	0	0
T64	5194	1	0	0
T97	41817	55	0	0
T99	96608	74	0	0
T216	8974	6	0	0
T259	2405	7	0	0
T278	7289	20	0	0
T280	5362	4	0	0
T281	7261	23	0	0
T282	18130	43	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2420	0	0
T63	10197	3	0	0
T64	5194	14	0	0
T97	41817	109	0	0
T99	96608	120	0	0
T216	8974	8	0	0
T259	2405	7	0	0
T278	7289	53	0	0
T279	9140	4	0	0
T280	5362	20	0	0
T281	7261	12	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1800	0	0
T63	10197	9	0	0
T97	41817	81	0	0
T99	96608	62	0	0
T216	8974	3	0	0
T278	7289	8	0	0
T279	9140	18	0	0
T280	5362	10	0	0
T281	7261	8	0	0
T282	18130	34	0	0
T283	5715	15	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2392	0	0
T63	10197	49	0	0
T64	5194	2	0	0
T97	41817	98	0	0
T99	96608	43	0	0
T216	8974	24	0	0
T259	2405	4	0	0
T278	7289	13	0	0
T279	9140	11	0	0
T280	5362	19	0	0
T281	7261	6	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2328	0	0
T63	10197	1	0	0
T97	41817	43	0	0
T99	96608	66	0	0
T216	8974	7	0	0
T278	7289	8	0	0
T279	9140	22	0	0
T280	5362	11	0	0
T281	7261	8	0	0
T282	18130	34	0	0
T283	5715	8	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1431	0	0
T63	10197	27	0	0
T64	5194	6	0	0
T97	41817	68	0	0
T99	96608	68	0	0
T216	8974	15	0	0
T278	7289	21	0	0
T280	5362	14	0	0
T281	7261	16	0	0
T282	18130	32	0	0
T283	5715	7	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2488	0	0
T63	10197	39	0	0
T97	41817	63	0	0
T99	96608	66	0	0
T216	8974	24	0	0
T278	7289	17	0	0
T279	9140	5	0	0
T280	5362	4	0	0
T281	7261	16	0	0
T282	18130	57	0	0
T283	5715	14	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2222	0	0
T63	10197	43	0	0
T64	5194	14	0	0
T97	41817	65	0	0
T99	96608	63	0	0
T216	8974	8	0	0
T278	7289	23	0	0
T280	5362	6	0	0
T281	7261	10	0	0
T282	18130	29	0	0
T283	5715	19	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2515	0	0
T63	10197	51	0	0
T64	5194	6	0	0
T97	41817	59	0	0
T99	96608	68	0	0
T216	8974	14	0	0
T278	7289	5	0	0
T279	9140	15	0	0
T280	5362	14	0	0
T281	7261	18	0	0
T282	18130	67	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2336	0	0
T63	10197	18	0	0
T64	5194	1	0	0
T97	41817	51	0	0
T99	96608	63	0	0
T216	8974	22	0	0
T278	7289	14	0	0
T279	9140	4	0	0
T280	5362	15	0	0
T281	7261	10	0	0
T282	18130	19	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2768	0	0
T63	10197	16	0	0
T64	5194	22	0	0
T97	41817	216	0	0
T99	96608	237	0	0
T216	8974	26	0	0
T278	7289	29	0	0
T279	9140	3	0	0
T280	5362	35	0	0
T281	7261	28	0	0
T282	18130	66	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2804	0	0
T63	10197	31	0	0
T97	41817	155	0	0
T99	96608	198	0	0
T216	8974	34	0	0
T259	2405	5	0	0
T278	7289	53	0	0
T279	9140	10	0	0
T280	5362	26	0	0
T281	7261	9	0	0
T282	18130	37	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1963	0	0
T63	10197	12	0	0
T64	5194	13	0	0
T97	41817	153	0	0
T99	96608	146	0	0
T216	8974	29	0	0
T259	2405	1	0	0
T278	7289	7	0	0
T280	5362	5	0	0
T281	7261	10	0	0
T282	18130	59	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2822	0	0
T63	10197	14	0	0
T64	5194	3	0	0
T97	41817	191	0	0
T99	96608	164	0	0
T216	8974	34	0	0
T259	2405	10	0	0
T278	7289	9	0	0
T279	9140	8	0	0
T280	5362	3	0	0
T281	7261	8	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2702	0	0
T64	5194	7	0	0
T97	41817	197	0	0
T99	96608	131	0	0
T216	8974	13	0	0
T259	2405	7	0	0
T278	7289	29	0	0
T279	9140	4	0	0
T280	5362	8	0	0
T281	7261	24	0	0
T282	18130	47	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2659	0	0
T63	10197	60	0	0
T64	5194	11	0	0
T97	41817	205	0	0
T99	96608	143	0	0
T216	8974	55	0	0
T278	7289	57	0	0
T279	9140	6	0	0
T280	5362	35	0	0
T281	7261	23	0	0
T282	18130	40	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2556	0	0
T63	10197	29	0	0
T64	5194	7	0	0
T97	41817	216	0	0
T99	96608	200	0	0
T216	8974	23	0	0
T278	7289	45	0	0
T280	5362	29	0	0
T281	7261	27	0	0
T282	18130	78	0	0
T283	5715	11	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2692	0	0
T63	10197	20	0	0
T64	5194	17	0	0
T97	41817	182	0	0
T99	96608	134	0	0
T216	8974	38	0	0
T259	2405	3	0	0
T278	7289	39	0	0
T279	9140	11	0	0
T280	5362	6	0	0
T281	7261	41	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1243	0	0
T63	10197	16	0	0
T64	5194	4	0	0
T216	8974	8	0	0
T259	2405	4	0	0
T279	9140	39	0	0
T280	5362	1	0	0
T282	18130	50	0	0
T283	5715	4	0	0
T284	10348	14	0	0
T285	20359	52	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1836	0	0
T64	5194	1	0	0
T97	41817	29	0	0
T99	96608	57	0	0
T216	8974	4	0	0
T259	2405	4	0	0
T278	7289	11	0	0
T279	9140	5	0	0
T280	5362	10	0	0
T281	7261	3	0	0
T282	18130	16	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1601	0	0
T63	10197	12	0	0
T64	5194	8	0	0
T97	41817	35	0	0
T99	96608	35	0	0
T216	8974	13	0	0
T259	2405	7	0	0
T278	7289	9	0	0
T279	9140	2	0	0
T280	5362	5	0	0
T281	7261	3	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1715	0	0
T63	10197	18	0	0
T97	41817	33	0	0
T99	96608	53	0	0
T216	8974	14	0	0
T259	2405	2	0	0
T278	7289	4	0	0
T279	9140	3	0	0
T280	5362	5	0	0
T281	7261	5	0	0
T282	18130	16	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2227	0	0
T63	10197	7	0	0
T64	5194	4	0	0
T97	41817	39	0	0
T99	96608	31	0	0
T216	8974	15	0	0
T259	2405	2	0	0
T278	7289	6	0	0
T279	9140	6	0	0
T280	5362	1	0	0
T281	7261	7	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1323	0	0
T63	10197	44	0	0
T64	5194	7	0	0
T97	41817	42	0	0
T99	96608	31	0	0
T216	8974	8	0	0
T259	2405	2	0	0
T278	7289	10	0	0
T279	9140	15	0	0
T280	5362	11	0	0
T281	7261	12	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1685	0	0
T63	10197	28	0	0
T97	41817	27	0	0
T99	96608	39	0	0
T216	8974	8	0	0
T278	7289	8	0	0
T280	5362	10	0	0
T281	7261	6	0	0
T282	18130	54	0	0
T283	5715	5	0	0
T284	10348	6	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2181	0	0
T63	10197	18	0	0
T64	5194	7	0	0
T97	41817	37	0	0
T99	96608	32	0	0
T278	7289	9	0	0
T279	9140	5	0	0
T280	5362	9	0	0
T281	7261	12	0	0
T282	18130	33	0	0
T283	5715	9	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	2124	0	0
T63	10197	1	0	0
T97	41817	25	0	0
T99	96608	44	0	0
T216	8974	15	0	0
T278	7289	4	0	0
T279	9140	16	0	0
T280	5362	16	0	0
T281	7261	6	0	0
T282	18130	38	0	0
T283	5715	14	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401690832	1764	0	0
T63	10197	2	0	0
T64	5194	4	0	0
T97	41817	50	0	0
T99	96608	62	0	0
T216	8974	19	0	0
T278	7289	8	0	0
T279	9140	4	0	0
T280	5362	5	0	0
T281	7261	6	0	0
T282	18130	25	0	0