SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 97.62 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block] | 92.86 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
92.86 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 92.86 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 1 | 3 | 75.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 29298882 | 1 | T1 | 488 | T2 | 145 | T3 | 6578 | |||
auto[1] | 5129497 | 1 | T1 | 11 | T3 | 9216 | T4 | 28368 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 34428192 | 1 | T1 | 499 | T2 | 145 | T3 | 15794 | |||
values[1] | 24 | 1 | T101 | 1 | T240 | 1 | T242 | 2 | |||
values[2] | 2 | 1 | T240 | 1 | T275 | 1 | - | - | |||
values[3] | 93 | 1 | T60 | 2 | T101 | 3 | T240 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 1 | 3 | 75.00 |
NAME | COUNT | AT LEAST | NUMBER |
values[2] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 34428196 | 1 | T1 | 499 | T2 | 145 | T3 | 15794 | |||
values[1] | 25 | 1 | T240 | 1 | T241 | 4 | T235 | 1 | |||
values[3] | 82 | 1 | T60 | 3 | T101 | 3 | T240 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 34428109 | 1 | T1 | 499 | T2 | 145 | T3 | 15794 | |||
auto[TlIntgErrCmd] | 87 | 1 | T60 | 5 | T101 | 3 | T240 | 1 | |||
auto[TlIntgErrData] | 83 | 1 | T60 | 5 | T101 | 4 | T240 | 2 | |||
auto[TlIntgErrBoth] | 100 | 1 | T101 | 3 | T240 | 7 | T241 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | |||
auto[1] | 4071340 | 0 | T6 | 16922 | T4 | 16950 | T19 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4071168 | 1 | T6 | 16922 | T4 | 16950 | T19 | 6 | |||
values[1] | 20 | 1 | T101 | 1 | T240 | 1 | T235 | 1 | |||
values[2] | 3 | 1 | T342 | 1 | T343 | 1 | T344 | 1 | |||
values[3] | 85 | 1 | T60 | 2 | T101 | 2 | T240 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 4071173 | 1 | T6 | 16922 | T4 | 16950 | T19 | 6 | |||
values[1] | 18 | 1 | T60 | 1 | T101 | 1 | T240 | 1 | |||
values[2] | 2 | 1 | T60 | 1 | T344 | 1 | - | - | |||
values[3] | 89 | 1 | T60 | 6 | T101 | 4 | T240 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 4071090 | 1 | T6 | 16922 | T4 | 16950 | T19 | 6 | |||
auto[TlIntgErrCmd] | 83 | 1 | T60 | 1 | T101 | 3 | T240 | 1 | |||
auto[TlIntgErrData] | 78 | 1 | T60 | 4 | T101 | 3 | T240 | 4 | |||
auto[TlIntgErrBoth] | 89 | 1 | T60 | 4 | T101 | 4 | T240 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 80480 | 0 | T58 | 42 | T60 | 676 | T101 | 654 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 80303 | 1 | T58 | 42 | T60 | 669 | T101 | 648 | |||
values[1] | 17 | 1 | T60 | 1 | T240 | 1 | T241 | 1 | |||
values[2] | 1 | 1 | T345 | 1 | - | - | - | - | |||
values[3] | 92 | 1 | T60 | 3 | T101 | 3 | T240 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 80294 | 1 | T58 | 42 | T60 | 669 | T101 | 644 | |||
values[1] | 23 | 1 | T60 | 1 | T241 | 1 | T235 | 1 | |||
values[2] | 7 | 1 | T242 | 1 | T346 | 1 | T347 | 1 | |||
values[3] | 88 | 1 | T60 | 3 | T101 | 4 | T240 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 80210 | 1 | T58 | 42 | T60 | 666 | T101 | 644 | |||
auto[TlIntgErrCmd] | 84 | 1 | T60 | 3 | T240 | 6 | T241 | 11 | |||
auto[TlIntgErrData] | 93 | 1 | T60 | 3 | T101 | 4 | T240 | 2 | |||
auto[TlIntgErrBoth] | 93 | 1 | T60 | 4 | T101 | 6 | T240 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |