Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26870834	1		T1	394		T2	62		T3	5799
full_word	7557545	1		T1	105		T2	83		T3	9995

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34428109	1		T1	499		T2	145		T3	15794
auto[TlIntgErrCmd]	87	1		T60	5		T101	3		T240	1
auto[TlIntgErrData]	83	1		T60	5		T101	4		T240	2
auto[TlIntgErrBoth]	100	1		T101	3		T240	7		T241	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30049462	1		T1	384		T2	57		T3	10857
auto[1]	4378917	1		T1	115		T2	88		T3	4937

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26208713	1		T1	382		T2	57		T3	5590
auto[TlIntgErrNone]	partial	auto[1]	661878	1		T1	12		T2	5		T3	209
auto[TlIntgErrNone]	full_word	auto[0]	3840626	1		T1	2		T3	5267		T6	1
auto[TlIntgErrNone]	full_word	auto[1]	3716892	1		T1	103		T2	83		T3	4728
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T60	3		T101	1		T241	4
auto[TlIntgErrCmd]	partial	auto[1]	45	1		T60	2		T101	2		T240	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T242	1		T344	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T235	1		T348	1		T345	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T60	4		T101	1		T240	1
auto[TlIntgErrData]	partial	auto[1]	34	1		T60	1		T101	3		T240	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T235	1		T349	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T241	1		T346	1		T275	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T101	1		T240	1		T241	4
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T101	2		T240	4		T241	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T240	2		T346	1		T345	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T346	3		T343	2		T349	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19813	1		T60	9		T101	9		T103	762
full_word	4051527	1		T6	16922		T4	16950		T19	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4071090	1		T6	16922		T4	16950		T19	6
auto[TlIntgErrCmd]	83	1		T60	1		T101	3		T240	1
auto[TlIntgErrData]	78	1		T60	4		T101	3		T240	4
auto[TlIntgErrBoth]	89	1		T60	4		T101	4		T240	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4046146	1		T6	16922		T4	16950		T19	6
auto[1]	25194	1		T60	4		T101	5		T103	926

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1412	1		T103	63		T205	95		T102	10
auto[TlIntgErrNone]	partial	auto[1]	18176	1		T103	699		T205	696		T102	147
auto[TlIntgErrNone]	full_word	auto[0]	4044628	1		T6	16922		T4	16950		T19	6
auto[TlIntgErrNone]	full_word	auto[1]	6874	1		T103	227		T205	120		T102	26
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T60	1		T241	3		T235	2
auto[TlIntgErrCmd]	partial	auto[1]	44	1		T101	2		T240	1		T241	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T346	1		T275	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T101	1		T235	1		T350	1
auto[TlIntgErrData]	partial	auto[0]	29	1		T60	2		T101	2		T240	1
auto[TlIntgErrData]	partial	auto[1]	41	1		T60	2		T101	1		T240	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T240	1		T275	1		T343	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T275	1		T343	1		T345	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T60	2		T101	3		T240	2
auto[TlIntgErrBoth]	partial	auto[1]	43	1		T60	2		T101	1		T240	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T351	1		T343	1		T352	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T240	1		T241	3		T351	1