Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1548346220	1545070484	0	0
CheckNGreaterZero_A	4176	4176	0	0
GntImpliesReady_A	1548346220	403541736	0	0
GntImpliesValid_A	1548346220	403541736	0	0
GrantKnown_A	1548346220	1545070484	0	0
IdxKnown_A	1548346220	1545070484	0	0
IndexIsCorrect_A	1548346220	403541736	0	0
NoReadyValidNoGrant_A	1548346220	175701282	0	0
Priority_A	1548346220	427677594	0	0
ReadyAndValidImplyGrant_A	1548346220	403541736	0	0
ReqAndReadyImplyGrant_A	1548346220	403541736	0	0
ReqImpliesValid_A	1548346220	427677594	0	0
ValidKnown_A	1548346220	1545070484	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	1545070484	0	0
T1	8480	8164	0	0
T2	25640	23256	0	0
T3	454164	453780	0	0
T4	677780	677204	0	0
T5	4060	3692	0	0
T6	2316760	2316144	0	0
T7	1139360	1139084	0	0
T11	14964	12516	0	0
T12	6092	5208	0	0
T19	13240	12556	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4176	4176	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	403541736	0	0
T1	8480	1378	0	0
T2	25640	1384	0	0
T3	454164	4680	0	0
T4	677780	90740	0	0
T5	4060	584	0	0
T6	2316760	33912	0	0
T7	1139360	390212	0	0
T8	0	132	0	0
T11	14964	284	0	0
T12	6092	134	0	0
T19	13240	844	0	0
T20	0	217600	0	0
T22	0	46	0	0
T31	0	39748	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	403541736	0	0
T1	8480	1378	0	0
T2	25640	1384	0	0
T3	454164	4680	0	0
T4	677780	90740	0	0
T5	4060	584	0	0
T6	2316760	33912	0	0
T7	1139360	390212	0	0
T8	0	132	0	0
T11	14964	284	0	0
T12	6092	134	0	0
T19	13240	844	0	0
T20	0	217600	0	0
T22	0	46	0	0
T31	0	39748	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	1545070484	0	0
T1	8480	8164	0	0
T2	25640	23256	0	0
T3	454164	453780	0	0
T4	677780	677204	0	0
T5	4060	3692	0	0
T6	2316760	2316144	0	0
T7	1139360	1139084	0	0
T11	14964	12516	0	0
T12	6092	5208	0	0
T19	13240	12556	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	1545070484	0	0
T1	8480	8164	0	0
T2	25640	23256	0	0
T3	454164	453780	0	0
T4	677780	677204	0	0
T5	4060	3692	0	0
T6	2316760	2316144	0	0
T7	1139360	1139084	0	0
T11	14964	12516	0	0
T12	6092	5208	0	0
T19	13240	12556	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	403541736	0	0
T1	8480	1378	0	0
T2	25640	1384	0	0
T3	454164	4680	0	0
T4	677780	90740	0	0
T5	4060	584	0	0
T6	2316760	33912	0	0
T7	1139360	390212	0	0
T8	0	132	0	0
T11	14964	284	0	0
T12	6092	134	0	0
T19	13240	844	0	0
T20	0	217600	0	0
T22	0	46	0	0
T31	0	39748	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	175701282	0	0
T1	4240	256	0	0
T2	25640	3298	0	0
T3	454164	7296	0	0
T4	677780	247918	0	0
T5	4060	256	0	0
T6	2316760	1255458	0	0
T7	1139360	164218	0	0
T11	14964	1084	0	0
T12	6092	536	0	0
T19	13240	1006	0	0
T22	0	126	0	0
T26	0	1051648	0	0
T31	0	108304	0	0
T40	0	25406	0	0
T44	2396	0	0	0
T50	0	1048576	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	427677594	0	0
T1	8480	1378	0	0
T2	25640	1384	0	0
T3	454164	4680	0	0
T4	677780	94674	0	0
T5	4060	584	0	0
T6	2316760	493958	0	0
T7	1139360	446196	0	0
T8	0	132	0	0
T11	14964	284	0	0
T12	6092	134	0	0
T19	13240	844	0	0
T20	0	217600	0	0
T22	0	46	0	0
T31	0	42182	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	403541736	0	0
T1	8480	1378	0	0
T2	25640	1384	0	0
T3	454164	4680	0	0
T4	677780	90740	0	0
T5	4060	584	0	0
T6	2316760	33912	0	0
T7	1139360	390212	0	0
T8	0	132	0	0
T11	14964	284	0	0
T12	6092	134	0	0
T19	13240	844	0	0
T20	0	217600	0	0
T22	0	46	0	0
T31	0	39748	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	403541736	0	0
T1	8480	1378	0	0
T2	25640	1384	0	0
T3	454164	4680	0	0
T4	677780	90740	0	0
T5	4060	584	0	0
T6	2316760	33912	0	0
T7	1139360	390212	0	0
T8	0	132	0	0
T11	14964	284	0	0
T12	6092	134	0	0
T19	13240	844	0	0
T20	0	217600	0	0
T22	0	46	0	0
T31	0	39748	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	427677594	0	0
T1	8480	1378	0	0
T2	25640	1384	0	0
T3	454164	4680	0	0
T4	677780	94674	0	0
T5	4060	584	0	0
T6	2316760	493958	0	0
T7	1139360	446196	0	0
T8	0	132	0	0
T11	14964	284	0	0
T12	6092	134	0	0
T19	13240	844	0	0
T20	0	217600	0	0
T22	0	46	0	0
T31	0	42182	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1548346220	1545070484	0	0
T1	8480	8164	0	0
T2	25640	23256	0	0
T3	454164	453780	0	0
T4	677780	677204	0	0
T5	4060	3692	0	0
T6	2316760	2316144	0	0
T7	1139360	1139084	0	0
T11	14964	12516	0	0
T12	6092	5208	0	0
T19	13240	12556	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387086555	386267621	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	387086555	109975154	0	0
GntImpliesValid_A	387086555	109975154	0	0
GrantKnown_A	387086555	386267621	0	0
IdxKnown_A	387086555	386267621	0	0
IndexIsCorrect_A	387086555	109975154	0	0
NoReadyValidNoGrant_A	387086555	46234235	0	0
Priority_A	387086555	116177141	0	0
ReadyAndValidImplyGrant_A	387086555	109975154	0	0
ReqAndReadyImplyGrant_A	387086555	109975154	0	0
ReqImpliesValid_A	387086555	116177141	0	0
ValidKnown_A	387086555	386267621	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	109975154	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	21282	0	0
T5	1015	292	0	0
T6	579190	8485	0	0
T7	284840	99630	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	109975154	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	21282	0	0
T5	1015	292	0	0
T6	579190	8485	0	0
T7	284840	99630	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	109975154	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	21282	0	0
T5	1015	292	0	0
T6	579190	8485	0	0
T7	284840	99630	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	46234235	0	0
T1	2120	128	0	0
T2	6410	943	0	0
T3	113541	3648	0	0
T4	169445	58481	0	0
T5	1015	128	0	0
T6	579190	314703	0	0
T7	284840	40438	0	0
T11	3741	542	0	0
T12	1523	268	0	0
T19	3310	447	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	116177141	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	22540	0	0
T5	1015	292	0	0
T6	579190	123024	0	0
T7	284840	111393	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	109975154	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	21282	0	0
T5	1015	292	0	0
T6	579190	8485	0	0
T7	284840	99630	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	109975154	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	21282	0	0
T5	1015	292	0	0
T6	579190	8485	0	0
T7	284840	99630	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	116177141	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	22540	0	0
T5	1015	292	0	0
T6	579190	123024	0	0
T7	284840	111393	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387086555	386267621	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	387086555	109975092	0	0
GntImpliesValid_A	387086555	109975092	0	0
GrantKnown_A	387086555	386267621	0	0
IdxKnown_A	387086555	386267621	0	0
IndexIsCorrect_A	387086555	109975092	0	0
NoReadyValidNoGrant_A	387086555	46234235	0	0
Priority_A	387086555	116177079	0	0
ReadyAndValidImplyGrant_A	387086555	109975092	0	0
ReqAndReadyImplyGrant_A	387086555	109975092	0	0
ReqImpliesValid_A	387086555	116177079	0	0
ValidKnown_A	387086555	386267621	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	109975092	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	21282	0	0
T5	1015	292	0	0
T6	579190	8485	0	0
T7	284840	99630	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	109975092	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	21282	0	0
T5	1015	292	0	0
T6	579190	8485	0	0
T7	284840	99630	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	109975092	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	21282	0	0
T5	1015	292	0	0
T6	579190	8485	0	0
T7	284840	99630	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	46234235	0	0
T1	2120	128	0	0
T2	6410	943	0	0
T3	113541	3648	0	0
T4	169445	58481	0	0
T5	1015	128	0	0
T6	579190	314703	0	0
T7	284840	40438	0	0
T11	3741	542	0	0
T12	1523	268	0	0
T19	3310	447	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	116177079	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	22540	0	0
T5	1015	292	0	0
T6	579190	123024	0	0
T7	284840	111393	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	109975092	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	21282	0	0
T5	1015	292	0	0
T6	579190	8485	0	0
T7	284840	99630	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	109975092	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	21282	0	0
T5	1015	292	0	0
T6	579190	8485	0	0
T7	284840	99630	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	116177079	0	0
T1	2120	201	0	0
T2	6410	292	0	0
T3	113541	2340	0	0
T4	169445	22540	0	0
T5	1015	292	0	0
T6	579190	123024	0	0
T7	284840	111393	0	0
T11	3741	142	0	0
T12	1523	67	0	0
T19	3310	332	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T19
1	0	Covered	T2,T6,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T4,T19
1	1	Covered	T2,T6,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T4,T19

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387086555	386267621	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	387086555	91795780	0	0
GntImpliesValid_A	387086555	91795780	0	0
GrantKnown_A	387086555	386267621	0	0
IdxKnown_A	387086555	386267621	0	0
IndexIsCorrect_A	387086555	91795780	0	0
NoReadyValidNoGrant_A	387086555	41616406	0	0
Priority_A	387086555	97661722	0	0
ReadyAndValidImplyGrant_A	387086555	91795780	0	0
ReqAndReadyImplyGrant_A	387086555	91795780	0	0
ReqImpliesValid_A	387086555	97661722	0	0
ValidKnown_A	387086555	386267621	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	91795780	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24088	0	0
T5	1015	0	0	0
T6	579190	8471	0	0
T7	284840	95476	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	19874	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	91795780	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24088	0	0
T5	1015	0	0	0
T6	579190	8471	0	0
T7	284840	95476	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	19874	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	91795780	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24088	0	0
T5	1015	0	0	0
T6	579190	8471	0	0
T7	284840	95476	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	19874	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	41616406	0	0
T2	6410	706	0	0
T3	113541	0	0	0
T4	169445	65478	0	0
T5	1015	0	0	0
T6	579190	313026	0	0
T7	284840	41671	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	56	0	0
T22	0	63	0	0
T26	0	525824	0	0
T31	0	54152	0	0
T40	0	12703	0	0
T44	1198	0	0	0
T50	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	97661722	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24797	0	0
T5	1015	0	0	0
T6	579190	123955	0	0
T7	284840	111705	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	21091	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	91795780	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24088	0	0
T5	1015	0	0	0
T6	579190	8471	0	0
T7	284840	95476	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	19874	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	91795780	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24088	0	0
T5	1015	0	0	0
T6	579190	8471	0	0
T7	284840	95476	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	19874	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	97661722	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24797	0	0
T5	1015	0	0	0
T6	579190	123955	0	0
T7	284840	111705	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	21091	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T19
1	0	Covered	T2,T6,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T6,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T4
1	0	Covered	T1,T4,T19
1	1	Covered	T2,T6,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T4,T19

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T6,T4
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T6,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	387086555	386267621	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	387086555	91795710	0	0
GntImpliesValid_A	387086555	91795710	0	0
GrantKnown_A	387086555	386267621	0	0
IdxKnown_A	387086555	386267621	0	0
IndexIsCorrect_A	387086555	91795710	0	0
NoReadyValidNoGrant_A	387086555	41616406	0	0
Priority_A	387086555	97661652	0	0
ReadyAndValidImplyGrant_A	387086555	91795710	0	0
ReqAndReadyImplyGrant_A	387086555	91795710	0	0
ReqImpliesValid_A	387086555	97661652	0	0
ValidKnown_A	387086555	386267621	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	91795710	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24088	0	0
T5	1015	0	0	0
T6	579190	8471	0	0
T7	284840	95476	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	19874	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	91795710	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24088	0	0
T5	1015	0	0	0
T6	579190	8471	0	0
T7	284840	95476	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	19874	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	91795710	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24088	0	0
T5	1015	0	0	0
T6	579190	8471	0	0
T7	284840	95476	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	19874	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	41616406	0	0
T2	6410	706	0	0
T3	113541	0	0	0
T4	169445	65478	0	0
T5	1015	0	0	0
T6	579190	313026	0	0
T7	284840	41671	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	56	0	0
T22	0	63	0	0
T26	0	525824	0	0
T31	0	54152	0	0
T40	0	12703	0	0
T44	1198	0	0	0
T50	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	97661652	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24797	0	0
T5	1015	0	0	0
T6	579190	123955	0	0
T7	284840	111705	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	21091	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	91795710	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24088	0	0
T5	1015	0	0	0
T6	579190	8471	0	0
T7	284840	95476	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	19874	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	91795710	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24088	0	0
T5	1015	0	0	0
T6	579190	8471	0	0
T7	284840	95476	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	19874	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	97661652	0	0
T1	2120	488	0	0
T2	6410	400	0	0
T3	113541	0	0	0
T4	169445	24797	0	0
T5	1015	0	0	0
T6	579190	123955	0	0
T7	284840	111705	0	0
T8	0	66	0	0
T11	3741	0	0	0
T12	1523	0	0	0
T19	3310	90	0	0
T20	0	108800	0	0
T22	0	23	0	0
T31	0	21091	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	387086555	386267621	0	0
T1	2120	2041	0	0
T2	6410	5814	0	0
T3	113541	113445	0	0
T4	169445	169301	0	0
T5	1015	923	0	0
T6	579190	579036	0	0
T7	284840	284771	0	0
T11	3741	3129	0	0
T12	1523	1302	0	0
T19	3310	3139	0	0