Line Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
flash_phy_rd_buffers
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T41,T73 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T22,T51,T61 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T6 |
Branch Coverage for Module :
flash_phy_rd_buffers
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T26,T41,T73 |
0 |
0 |
1 |
- |
- |
Covered |
T22,T51,T61 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
flash_phy_rd_buffers
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5181227 |
0 |
0 |
T2 |
51280 |
127 |
0 |
0 |
T3 |
908328 |
1024 |
0 |
0 |
T4 |
1355560 |
31732 |
0 |
0 |
T5 |
8120 |
0 |
0 |
0 |
T6 |
4633520 |
16921 |
0 |
0 |
T7 |
2278720 |
46222 |
0 |
0 |
T11 |
29928 |
0 |
0 |
0 |
T12 |
12184 |
0 |
0 |
0 |
T19 |
26480 |
58 |
0 |
0 |
T22 |
0 |
41 |
0 |
0 |
T26 |
0 |
2560 |
0 |
0 |
T31 |
0 |
30236 |
0 |
0 |
T32 |
0 |
16719 |
0 |
0 |
T40 |
0 |
18876 |
0 |
0 |
T44 |
9584 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
5181220 |
0 |
0 |
T2 |
51280 |
127 |
0 |
0 |
T3 |
908328 |
1024 |
0 |
0 |
T4 |
1355560 |
31732 |
0 |
0 |
T5 |
8120 |
0 |
0 |
0 |
T6 |
4633520 |
16921 |
0 |
0 |
T7 |
2278720 |
46222 |
0 |
0 |
T11 |
29928 |
0 |
0 |
0 |
T12 |
12184 |
0 |
0 |
0 |
T19 |
26480 |
58 |
0 |
0 |
T22 |
0 |
41 |
0 |
0 |
T26 |
0 |
2560 |
0 |
0 |
T31 |
0 |
30236 |
0 |
0 |
T32 |
0 |
16719 |
0 |
0 |
T40 |
0 |
18876 |
0 |
0 |
T44 |
9584 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T41,T39 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T51,T61,T74 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T26,T41,T39 |
0 |
0 |
1 |
- |
- |
Covered |
T51,T61,T74 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
725509 |
0 |
0 |
T2 |
6410 |
7 |
0 |
0 |
T3 |
113541 |
256 |
0 |
0 |
T4 |
169445 |
3766 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2113 |
0 |
0 |
T7 |
284840 |
5590 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
11 |
0 |
0 |
T22 |
0 |
7 |
0 |
0 |
T26 |
0 |
512 |
0 |
0 |
T31 |
0 |
3843 |
0 |
0 |
T40 |
0 |
2386 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
725509 |
0 |
0 |
T2 |
6410 |
7 |
0 |
0 |
T3 |
113541 |
256 |
0 |
0 |
T4 |
169445 |
3766 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2113 |
0 |
0 |
T7 |
284840 |
5590 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
11 |
0 |
0 |
T22 |
0 |
7 |
0 |
0 |
T26 |
0 |
512 |
0 |
0 |
T31 |
0 |
3843 |
0 |
0 |
T40 |
0 |
2386 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T41,T39 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T22,T51,T61 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T26,T41,T39 |
0 |
0 |
1 |
- |
- |
Covered |
T22,T51,T61 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
725429 |
0 |
0 |
T2 |
6410 |
6 |
0 |
0 |
T3 |
113541 |
256 |
0 |
0 |
T4 |
169445 |
3767 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2113 |
0 |
0 |
T7 |
284840 |
5591 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
11 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
512 |
0 |
0 |
T31 |
0 |
3853 |
0 |
0 |
T40 |
0 |
2389 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
725428 |
0 |
0 |
T2 |
6410 |
6 |
0 |
0 |
T3 |
113541 |
256 |
0 |
0 |
T4 |
169445 |
3767 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2113 |
0 |
0 |
T7 |
284840 |
5591 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
11 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
512 |
0 |
0 |
T31 |
0 |
3853 |
0 |
0 |
T40 |
0 |
2389 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T41,T39 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T51,T61,T74 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T26,T41,T39 |
0 |
0 |
1 |
- |
- |
Covered |
T51,T61,T74 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
725269 |
0 |
0 |
T2 |
6410 |
6 |
0 |
0 |
T3 |
113541 |
256 |
0 |
0 |
T4 |
169445 |
3760 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2112 |
0 |
0 |
T7 |
284840 |
5588 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
11 |
0 |
0 |
T22 |
0 |
6 |
0 |
0 |
T26 |
0 |
512 |
0 |
0 |
T31 |
0 |
3858 |
0 |
0 |
T40 |
0 |
2387 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
725268 |
0 |
0 |
T2 |
6410 |
6 |
0 |
0 |
T3 |
113541 |
256 |
0 |
0 |
T4 |
169445 |
3760 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2112 |
0 |
0 |
T7 |
284840 |
5588 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
11 |
0 |
0 |
T22 |
0 |
6 |
0 |
0 |
T26 |
0 |
512 |
0 |
0 |
T31 |
0 |
3858 |
0 |
0 |
T40 |
0 |
2387 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T41,T39 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T6 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T51,T61,T74 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T6 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T6 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T26,T41,T39 |
0 |
0 |
1 |
- |
- |
Covered |
T51,T61,T74 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
725049 |
0 |
0 |
T2 |
6410 |
6 |
0 |
0 |
T3 |
113541 |
256 |
0 |
0 |
T4 |
169445 |
3762 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2112 |
0 |
0 |
T7 |
284840 |
5587 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
11 |
0 |
0 |
T22 |
0 |
6 |
0 |
0 |
T26 |
0 |
512 |
0 |
0 |
T31 |
0 |
3850 |
0 |
0 |
T40 |
0 |
2386 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
725049 |
0 |
0 |
T2 |
6410 |
6 |
0 |
0 |
T3 |
113541 |
256 |
0 |
0 |
T4 |
169445 |
3762 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2112 |
0 |
0 |
T7 |
284840 |
5587 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
11 |
0 |
0 |
T22 |
0 |
6 |
0 |
0 |
T26 |
0 |
512 |
0 |
0 |
T31 |
0 |
3850 |
0 |
0 |
T40 |
0 |
2386 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T6,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T73,T39 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T6,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T51,T63,T75 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T6,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T6,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T26,T73,T39 |
0 |
0 |
1 |
- |
- |
Covered |
T51,T63,T75 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T6,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T6,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
570300 |
0 |
0 |
T2 |
6410 |
28 |
0 |
0 |
T3 |
113541 |
0 |
0 |
0 |
T4 |
169445 |
4172 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2118 |
0 |
0 |
T7 |
284840 |
5968 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
4 |
0 |
0 |
T22 |
0 |
4 |
0 |
0 |
T26 |
0 |
128 |
0 |
0 |
T31 |
0 |
3709 |
0 |
0 |
T32 |
0 |
4184 |
0 |
0 |
T40 |
0 |
2331 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
570300 |
0 |
0 |
T2 |
6410 |
28 |
0 |
0 |
T3 |
113541 |
0 |
0 |
0 |
T4 |
169445 |
4172 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2118 |
0 |
0 |
T7 |
284840 |
5968 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
4 |
0 |
0 |
T22 |
0 |
4 |
0 |
0 |
T26 |
0 |
128 |
0 |
0 |
T31 |
0 |
3709 |
0 |
0 |
T32 |
0 |
4184 |
0 |
0 |
T40 |
0 |
2331 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T6,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T73,T39 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T6,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T51,T63,T75 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T6,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T6,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T26,T73,T39 |
0 |
0 |
1 |
- |
- |
Covered |
T51,T63,T75 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T6,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T6,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
570084 |
0 |
0 |
T2 |
6410 |
26 |
0 |
0 |
T3 |
113541 |
0 |
0 |
0 |
T4 |
169445 |
4166 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2118 |
0 |
0 |
T7 |
284840 |
5973 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
4 |
0 |
0 |
T22 |
0 |
4 |
0 |
0 |
T26 |
0 |
128 |
0 |
0 |
T31 |
0 |
3706 |
0 |
0 |
T32 |
0 |
4172 |
0 |
0 |
T40 |
0 |
2334 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
570083 |
0 |
0 |
T2 |
6410 |
26 |
0 |
0 |
T3 |
113541 |
0 |
0 |
0 |
T4 |
169445 |
4166 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2118 |
0 |
0 |
T7 |
284840 |
5973 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
4 |
0 |
0 |
T22 |
0 |
4 |
0 |
0 |
T26 |
0 |
128 |
0 |
0 |
T31 |
0 |
3706 |
0 |
0 |
T32 |
0 |
4172 |
0 |
0 |
T40 |
0 |
2334 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T6,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T73,T39 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T6,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T51,T63,T75 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T6,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T6,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T26,T73,T39 |
0 |
0 |
1 |
- |
- |
Covered |
T51,T63,T75 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T6,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T6,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
569995 |
0 |
0 |
T2 |
6410 |
24 |
0 |
0 |
T3 |
113541 |
0 |
0 |
0 |
T4 |
169445 |
4173 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2118 |
0 |
0 |
T7 |
284840 |
5961 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
3 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T26 |
0 |
128 |
0 |
0 |
T31 |
0 |
3716 |
0 |
0 |
T32 |
0 |
4184 |
0 |
0 |
T40 |
0 |
2330 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
569994 |
0 |
0 |
T2 |
6410 |
24 |
0 |
0 |
T3 |
113541 |
0 |
0 |
0 |
T4 |
169445 |
4173 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2118 |
0 |
0 |
T7 |
284840 |
5961 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
3 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T26 |
0 |
128 |
0 |
0 |
T31 |
0 |
3716 |
0 |
0 |
T32 |
0 |
4184 |
0 |
0 |
T40 |
0 |
2330 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 38 | 23 | 23 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
54 |
1 |
1 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Total | Covered | Percent |
Conditions | 14 | 11 | 78.57 |
Logical | 14 | 11 | 78.57 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
----1---- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T6,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T73,T39 |
LINE 45
SUB-EXPRESSION (out_o.attr != Invalid)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T6,T4 |
LINE 48
EXPRESSION (wipe_i && en_i)
---1-- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T51,T63,T75 |
LINE 51
EXPRESSION (alloc_i && en_i)
---1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T6,T4 |
LINE 57
EXPRESSION (update_i && en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T6,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
IF |
38 |
6 |
6 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 38 if ((!rst_ni))
-2-: 45 if (((!en_i) && (out_o.attr != Invalid)))
-3-: 48 if ((wipe_i && en_i))
-4-: 51 if ((alloc_i && en_i))
-5-: 57 if ((update_i && en_i))
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
- |
Covered |
T26,T73,T39 |
0 |
0 |
1 |
- |
- |
Covered |
T51,T63,T75 |
0 |
0 |
0 |
1 |
- |
Covered |
T2,T6,T4 |
0 |
0 |
0 |
0 |
1 |
Covered |
T2,T6,T4 |
0 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Assertion Details
AllocCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
569592 |
0 |
0 |
T2 |
6410 |
24 |
0 |
0 |
T3 |
113541 |
0 |
0 |
0 |
T4 |
169445 |
4166 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2117 |
0 |
0 |
T7 |
284840 |
5964 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
3 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T26 |
0 |
128 |
0 |
0 |
T31 |
0 |
3701 |
0 |
0 |
T32 |
0 |
4179 |
0 |
0 |
T40 |
0 |
2333 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |
UpdateCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
387086555 |
569589 |
0 |
0 |
T2 |
6410 |
24 |
0 |
0 |
T3 |
113541 |
0 |
0 |
0 |
T4 |
169445 |
4166 |
0 |
0 |
T5 |
1015 |
0 |
0 |
0 |
T6 |
579190 |
2117 |
0 |
0 |
T7 |
284840 |
5964 |
0 |
0 |
T11 |
3741 |
0 |
0 |
0 |
T12 |
1523 |
0 |
0 |
0 |
T19 |
3310 |
3 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T26 |
0 |
128 |
0 |
0 |
T31 |
0 |
3701 |
0 |
0 |
T32 |
0 |
4179 |
0 |
0 |
T40 |
0 |
2333 |
0 |
0 |
T44 |
1198 |
0 |
0 |
0 |