Line Coverage for Module :
flash_mp_data_region_sel ( parameter Regions=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
ALWAYS | 35 | 0 | 0 | |
ALWAYS | 35 | 3 | 3 | 100.00 |
ALWAYS | 49 | 4 | 4 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
30 |
8 |
8 |
35 |
1 |
1 |
36 |
1 |
1 |
39 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
Line Coverage for Module :
flash_mp_data_region_sel ( parameter Regions=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
ALWAYS | 35 | 0 | 0 | |
ALWAYS | 35 | 3 | 3 | 100.00 |
ALWAYS | 49 | 4 | 4 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
35 |
1 |
1 |
36 |
1 |
1 |
39 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
flash_mp_data_region_sel
| Total | Covered | Percent |
Conditions | 24 | 24 | 100.00 |
Logical | 24 | 24 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 30
EXPRESSION (region_match[1] & ((~|region_match[0])))
-------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T29,T213 |
1 | 1 | Covered | T2,T19,T31 |
LINE 30
EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T19,T267,T75 |
1 | 1 | Covered | T7,T31,T22 |
LINE 30
EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T61,T75,T133 |
1 | 1 | Covered | T4,T5,T7 |
LINE 30
EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T227,T163 |
1 | 1 | Covered | T7,T31,T22 |
LINE 30
EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T40,T61,T100 |
1 | 1 | Covered | T19,T31,T40 |
LINE 30
EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T204,T267,T75 |
1 | 1 | Covered | T19,T7,T40 |
LINE 30
EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T22,T100,T75 |
1 | 1 | Covered | T22,T40,T51 |
LINE 30
EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T5 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
flash_mp_data_region_sel
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 51 if (region_sel[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
ALWAYS | 35 | 0 | 0 | |
ALWAYS | 35 | 3 | 3 | 100.00 |
ALWAYS | 49 | 4 | 4 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
30 |
8 |
8 |
35 |
1 |
1 |
36 |
1 |
1 |
39 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
| Total | Covered | Percent |
Conditions | 24 | 24 | 100.00 |
Logical | 24 | 24 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 30
EXPRESSION (region_match[1] & ((~|region_match[0])))
-------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T213,T124 |
1 | 1 | Covered | T19,T61,T280 |
LINE 30
EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T19,T267,T75 |
1 | 1 | Covered | T7,T22,T51 |
LINE 30
EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T61,T75,T133 |
1 | 1 | Covered | T5,T7,T31 |
LINE 30
EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T227,T163 |
1 | 1 | Covered | T7,T31,T22 |
LINE 30
EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T40,T61,T100 |
1 | 1 | Covered | T31,T61,T63 |
LINE 30
EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T204,T267,T75 |
1 | 1 | Covered | T19,T7,T40 |
LINE 30
EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T100,T75,T133 |
1 | 1 | Covered | T51,T61,T280 |
LINE 30
EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T5,T19 |
1 | 1 | Covered | T1,T3,T4 |
Branch Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 51 if (region_sel[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
ALWAYS | 35 | 0 | 0 | |
ALWAYS | 35 | 3 | 3 | 100.00 |
ALWAYS | 49 | 4 | 4 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
35 |
1 |
1 |
36 |
1 |
1 |
39 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 51 if (region_sel[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T11,T26,T50 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_eflash.u_region_sel
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
ALWAYS | 35 | 0 | 0 | |
ALWAYS | 35 | 3 | 3 | 100.00 |
ALWAYS | 49 | 4 | 4 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
28 |
1 |
1 |
30 |
8 |
8 |
35 |
1 |
1 |
36 |
1 |
1 |
39 |
1 |
1 |
49 |
1 |
1 |
50 |
1 |
1 |
51 |
1 |
1 |
52 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_eflash.u_region_sel
| Total | Covered | Percent |
Conditions | 24 | 24 | 100.00 |
Logical | 24 | 24 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 30
EXPRESSION (region_match[1] & ((~|region_match[0])))
-------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T29,T213,T281 |
1 | 1 | Covered | T2,T31,T76 |
LINE 30
EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T282,T258,T283 |
1 | 1 | Covered | T31,T204,T209 |
LINE 30
EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T284,T285,T71 |
1 | 1 | Covered | T4,T22,T90 |
LINE 30
EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T284,T286,T287 |
1 | 1 | Covered | T90,T36,T76 |
LINE 30
EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T40,T288,T289 |
1 | 1 | Covered | T19,T31,T40 |
LINE 30
EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T37,T290,T286 |
1 | 1 | Covered | T19,T40,T57 |
LINE 30
EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T22,T286,T291 |
1 | 1 | Covered | T22,T40,T35 |
LINE 30
EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
-------1------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T4,T19 |
1 | 1 | Covered | T2,T6,T4 |
Branch Coverage for Instance : tb.dut.u_eflash.u_region_sel
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
51 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 51 if (region_sel[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T6,T4 |
0 |
Covered |
T1,T2,T3 |