SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[0].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[1].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
95.24 | 85.71 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
gen_info_types[2].u_info_mem |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T3,T11 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 8352 | 8352 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 2147483647 | 159778731 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 8352 | 8352 | 0 | 0 |
T1 | 8 | 8 | 0 | 0 |
T2 | 8 | 8 | 0 | 0 |
T3 | 8 | 8 | 0 | 0 |
T4 | 8 | 8 | 0 | 0 |
T5 | 8 | 8 | 0 | 0 |
T6 | 8 | 8 | 0 | 0 |
T7 | 8 | 8 | 0 | 0 |
T11 | 8 | 8 | 0 | 0 |
T12 | 8 | 8 | 0 | 0 |
T19 | 8 | 8 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 159778731 | 0 | 0 |
T3 | 113541 | 256 | 0 | 0 |
T4 | 169445 | 0 | 0 | 0 |
T5 | 1015 | 0 | 0 | 0 |
T6 | 579190 | 0 | 0 | 0 |
T7 | 284840 | 5450 | 0 | 0 |
T8 | 979 | 0 | 0 | 0 |
T11 | 3741 | 3 | 0 | 0 |
T12 | 1523 | 0 | 0 | 0 |
T19 | 3310 | 0 | 0 | 0 |
T20 | 214998 | 223500 | 0 | 0 |
T26 | 0 | 9216 | 0 | 0 |
T38 | 0 | 131222 | 0 | 0 |
T42 | 46242 | 0 | 0 | 0 |
T44 | 1198 | 0 | 0 | 0 |
T50 | 0 | 4864 | 0 | 0 |
T57 | 0 | 400 | 0 | 0 |
T61 | 772459 | 1675520 | 0 | 0 |
T64 | 4109 | 0 | 0 | 0 |
T74 | 253186 | 137712 | 0 | 0 |
T91 | 415022 | 0 | 0 | 0 |
T97 | 262900 | 0 | 0 | 0 |
T100 | 1902 | 50 | 0 | 0 |
T107 | 0 | 9 | 0 | 0 |
T121 | 0 | 650 | 0 | 0 |
T122 | 0 | 606 | 0 | 0 |
T123 | 0 | 458752 | 0 | 0 |
T124 | 0 | 327680 | 0 | 0 |
T125 | 0 | 458752 | 0 | 0 |
T126 | 0 | 65536 | 0 | 0 |
T127 | 0 | 12800 | 0 | 0 |
T128 | 0 | 12800 | 0 | 0 |
T129 | 0 | 256 | 0 | 0 |
T130 | 231206 | 0 | 0 | 0 |
T131 | 1369 | 0 | 0 | 0 |
T132 | 2333 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T5,T19 |
1 | 0 | Covered | T1,T2,T6 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 387086555 | 64004422 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 387086555 | 64004422 | 0 | 0 |
T1 | 2120 | 150 | 0 | 0 |
T2 | 6410 | 0 | 0 | 0 |
T3 | 113541 | 0 | 0 | 0 |
T4 | 169445 | 0 | 0 | 0 |
T5 | 1015 | 256 | 0 | 0 |
T6 | 579190 | 0 | 0 | 0 |
T7 | 284840 | 70950 | 0 | 0 |
T11 | 3741 | 0 | 0 | 0 |
T12 | 1523 | 0 | 0 | 0 |
T19 | 3310 | 150 | 0 | 0 |
T20 | 0 | 706500 | 0 | 0 |
T22 | 0 | 50 | 0 | 0 |
T23 | 0 | 50 | 0 | 0 |
T26 | 0 | 460032 | 0 | 0 |
T50 | 0 | 393219 | 0 | 0 |
T51 | 0 | 340034 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T3,T11,T7 |
1 | 0 | Covered | T1,T2,T3 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 387086555 | 13848000 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 387086555 | 13848000 | 0 | 0 |
T3 | 113541 | 256 | 0 | 0 |
T4 | 169445 | 0 | 0 | 0 |
T5 | 1015 | 0 | 0 | 0 |
T6 | 579190 | 0 | 0 | 0 |
T7 | 284840 | 5450 | 0 | 0 |
T8 | 979 | 0 | 0 | 0 |
T11 | 3741 | 3 | 0 | 0 |
T12 | 1523 | 0 | 0 | 0 |
T19 | 3310 | 0 | 0 | 0 |
T20 | 0 | 219500 | 0 | 0 |
T26 | 0 | 9216 | 0 | 0 |
T44 | 1198 | 0 | 0 | 0 |
T50 | 0 | 4864 | 0 | 0 |
T61 | 0 | 626944 | 0 | 0 |
T74 | 0 | 137712 | 0 | 0 |
T100 | 0 | 50 | 0 | 0 |
T107 | 0 | 9 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T61,T38,T122 |
1 | 0 | Covered | T33,T57,T35 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 387086555 | 3656542 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 387086555 | 3656542 | 0 | 0 |
T38 | 0 | 65536 | 0 | 0 |
T42 | 46242 | 0 | 0 | 0 |
T61 | 772459 | 524288 | 0 | 0 |
T64 | 4109 | 0 | 0 | 0 |
T74 | 253186 | 0 | 0 | 0 |
T91 | 415022 | 0 | 0 | 0 |
T97 | 262900 | 0 | 0 | 0 |
T100 | 1902 | 0 | 0 | 0 |
T122 | 0 | 606 | 0 | 0 |
T123 | 0 | 458752 | 0 | 0 |
T124 | 0 | 327680 | 0 | 0 |
T125 | 0 | 458752 | 0 | 0 |
T126 | 0 | 65536 | 0 | 0 |
T127 | 0 | 12800 | 0 | 0 |
T128 | 0 | 12800 | 0 | 0 |
T129 | 0 | 256 | 0 | 0 |
T130 | 231206 | 0 | 0 | 0 |
T131 | 1369 | 0 | 0 | 0 |
T132 | 2333 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T20,T61,T121 |
1 | 0 | Covered | T19,T7,T20 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 387086555 | 3778578 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 387086555 | 3778578 | 0 | 0 |
T20 | 214998 | 4000 | 0 | 0 |
T22 | 1847 | 0 | 0 | 0 |
T24 | 0 | 10000 | 0 | 0 |
T26 | 405237 | 0 | 0 | 0 |
T31 | 154524 | 0 | 0 | 0 |
T32 | 124114 | 0 | 0 | 0 |
T38 | 0 | 65686 | 0 | 0 |
T40 | 43056 | 0 | 0 | 0 |
T50 | 401263 | 0 | 0 | 0 |
T57 | 0 | 400 | 0 | 0 |
T61 | 0 | 524288 | 0 | 0 |
T76 | 0 | 100 | 0 | 0 |
T98 | 1505 | 0 | 0 | 0 |
T110 | 1195 | 0 | 0 | 0 |
T119 | 0 | 2150 | 0 | 0 |
T121 | 0 | 650 | 0 | 0 |
T133 | 0 | 250 | 0 | 0 |
T134 | 0 | 750 | 0 | 0 |
T135 | 1487 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T1,T7,T8 |
1 | 0 | Covered | T1,T2,T6 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 387086555 | 56946519 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 387086555 | 56946519 | 0 | 0 |
T1 | 2120 | 456 | 0 | 0 |
T2 | 6410 | 0 | 0 | 0 |
T3 | 113541 | 0 | 0 | 0 |
T4 | 169445 | 0 | 0 | 0 |
T5 | 1015 | 0 | 0 | 0 |
T6 | 579190 | 0 | 0 | 0 |
T7 | 284840 | 76700 | 0 | 0 |
T8 | 0 | 50 | 0 | 0 |
T11 | 3741 | 0 | 0 | 0 |
T12 | 1523 | 0 | 0 | 0 |
T19 | 3310 | 0 | 0 | 0 |
T20 | 0 | 979000 | 0 | 0 |
T26 | 0 | 460032 | 0 | 0 |
T50 | 0 | 393216 | 0 | 0 |
T51 | 0 | 77360 | 0 | 0 |
T61 | 0 | 4036 | 0 | 0 |
T114 | 0 | 150 | 0 | 0 |
T132 | 0 | 100 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T19,T51,T61 |
1 | 0 | Covered | T19,T22,T51 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 387086555 | 6485936 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 387086555 | 6485936 | 0 | 0 |
T7 | 284840 | 0 | 0 | 0 |
T8 | 979 | 0 | 0 | 0 |
T19 | 3310 | 50 | 0 | 0 |
T20 | 214998 | 0 | 0 | 0 |
T22 | 1847 | 0 | 0 | 0 |
T26 | 405237 | 0 | 0 | 0 |
T31 | 154524 | 0 | 0 | 0 |
T38 | 0 | 550 | 0 | 0 |
T44 | 1198 | 0 | 0 | 0 |
T50 | 401263 | 0 | 0 | 0 |
T51 | 0 | 300 | 0 | 0 |
T61 | 0 | 51456 | 0 | 0 |
T110 | 1195 | 0 | 0 | 0 |
T136 | 0 | 38800 | 0 | 0 |
T137 | 0 | 606 | 0 | 0 |
T138 | 0 | 256 | 0 | 0 |
T139 | 0 | 150 | 0 | 0 |
T140 | 0 | 256 | 0 | 0 |
T141 | 0 | 50 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T142,T123,T125 |
1 | 0 | Covered | T38,T142,T143 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 387086555 | 5519236 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 387086555 | 5519236 | 0 | 0 |
T77 | 38466 | 0 | 0 | 0 |
T122 | 97499 | 0 | 0 | 0 |
T123 | 0 | 196608 | 0 | 0 |
T125 | 0 | 589824 | 0 | 0 |
T142 | 161129 | 606 | 0 | 0 |
T144 | 0 | 12800 | 0 | 0 |
T145 | 0 | 524588 | 0 | 0 |
T146 | 0 | 524288 | 0 | 0 |
T147 | 0 | 720896 | 0 | 0 |
T148 | 0 | 524288 | 0 | 0 |
T149 | 0 | 720896 | 0 | 0 |
T150 | 0 | 506 | 0 | 0 |
T151 | 190638 | 0 | 0 | 0 |
T152 | 3825 | 0 | 0 | 0 |
T153 | 122994 | 0 | 0 | 0 |
T154 | 388196 | 0 | 0 | 0 |
T155 | 2625 | 0 | 0 | 0 |
T156 | 209479 | 0 | 0 | 0 |
T157 | 962731 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 7 | 6 | 85.71 | |
CONT_ASSIGN | 42 | 1 | 0 | 0.00 |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 63 | 6 | 6 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
42 | 0 | 1 | |
52 | unreachable | ||
63 | 1 | 1 | |
64 | 1 | 1 | |
65 | 1 | 1 | |
66 | 1 | 1 | |
67 | 1 | 1 | |
==> MISSING_ELSE | |||
72 | 1 | 1 | |
MISSING_ELSE |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
Branches | 3 | 3 | 100.00 | |
IF | 63 | 3 | 3 | 100.00 |
LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)
-1- | -2- | Status | Tests |
---|---|---|---|
1 | 1 | Covered | T38,T139,T123 |
1 | 0 | Covered | T38,T139,T143 |
0 | - | Covered | T1,T2,T3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
DataBitsPerMaskCheck_A | 1044 | 1044 | 0 | 0 |
gen_wmask[0].MaskCheck_A | 387086555 | 5539498 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 387086555 | 5539498 | 0 | 0 |
T24 | 197001 | 0 | 0 | 0 |
T38 | 74377 | 400 | 0 | 0 |
T65 | 3689 | 0 | 0 | 0 |
T73 | 1049 | 0 | 0 | 0 |
T117 | 1146 | 0 | 0 | 0 |
T118 | 288139 | 0 | 0 | 0 |
T119 | 409808 | 0 | 0 | 0 |
T120 | 71725 | 0 | 0 | 0 |
T123 | 0 | 196608 | 0 | 0 |
T125 | 0 | 589824 | 0 | 0 |
T126 | 0 | 750 | 0 | 0 |
T139 | 0 | 256 | 0 | 0 |
T143 | 0 | 1700 | 0 | 0 |
T144 | 0 | 25600 | 0 | 0 |
T145 | 0 | 524288 | 0 | 0 |
T158 | 0 | 200 | 0 | 0 |
T159 | 0 | 450 | 0 | 0 |
T160 | 1270 | 0 | 0 | 0 |
T161 | 1508 | 0 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |