SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_seed_hw_rd_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_flash_hw_if.u_sync_rma_req | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prog_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_escalation_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tl_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_eflash.u_lc_nvm_debug_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
52.96 | 52.96 | u_region_cfg |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.69 | 97.12 | 93.60 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
97.17 | 100.00 | 94.79 | 92.11 | 98.94 | 100.00 | u_flash_hw_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.37 | 100.00 | 88.89 | 57.14 | 95.83 | 50.00 | u_prog_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.69 | 97.12 | 93.60 | 98.44 | 100.00 | 84.29 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
80.60 | 100.00 | 100.00 | 57.14 | 95.83 | 50.00 | u_tl_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.56 | 97.67 | 86.00 | 100.00 | u_eflash |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 10440 | 10440 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 21642 |
gen_no_flops.OutputDelay_A | 762945784 | 761307916 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10440 | 10440 | 0 | 0 |
T1 | 10 | 10 | 0 | 0 |
T2 | 10 | 10 | 0 | 0 |
T3 | 10 | 10 | 0 | 0 |
T4 | 10 | 10 | 0 | 0 |
T5 | 10 | 10 | 0 | 0 |
T6 | 10 | 10 | 0 | 0 |
T7 | 10 | 10 | 0 | 0 |
T11 | 10 | 10 | 0 | 0 |
T12 | 10 | 10 | 0 | 0 |
T19 | 10 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 21200 | 20410 | 0 | 0 |
T2 | 64100 | 58140 | 0 | 0 |
T3 | 3700 | 2740 | 0 | 0 |
T4 | 1694450 | 1693010 | 0 | 0 |
T5 | 9618 | 8698 | 0 | 0 |
T6 | 5791900 | 5790360 | 0 | 0 |
T7 | 2848400 | 2847710 | 0 | 0 |
T11 | 37410 | 31290 | 0 | 0 |
T12 | 15230 | 13020 | 0 | 0 |
T19 | 33100 | 31390 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 21642 |
T1 | 16960 | 16304 | 0 | 24 |
T2 | 51280 | 46344 | 0 | 24 |
T3 | 2960 | 2192 | 0 | 0 |
T4 | 1355560 | 1354360 | 0 | 24 |
T5 | 7588 | 6831 | 0 | 21 |
T6 | 4633520 | 4632240 | 0 | 24 |
T7 | 2278720 | 2278144 | 0 | 24 |
T8 | 0 | 0 | 0 | 24 |
T11 | 29928 | 24816 | 0 | 24 |
T12 | 12184 | 10344 | 0 | 24 |
T19 | 26480 | 25064 | 0 | 24 |
T20 | 0 | 0 | 0 | 3 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 762945784 | 761307916 | 0 | 0 |
T1 | 4240 | 4082 | 0 | 0 |
T2 | 12820 | 11628 | 0 | 0 |
T3 | 740 | 548 | 0 | 0 |
T4 | 338890 | 338602 | 0 | 0 |
T5 | 2030 | 1846 | 0 | 0 |
T6 | 1158380 | 1158072 | 0 | 0 |
T7 | 569680 | 569542 | 0 | 0 |
T11 | 7482 | 6258 | 0 | 0 |
T12 | 3046 | 2604 | 0 | 0 |
T19 | 6620 | 6278 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 381473027 | 380654093 | 0 | 0 |
gen_flops.OutputDelay_A | 381473027 | 380621966 | 0 | 2724 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380654093 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 1015 | 923 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380621966 | 0 | 2724 |
T1 | 2120 | 2038 | 0 | 3 |
T2 | 6410 | 5793 | 0 | 3 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169295 | 0 | 3 |
T5 | 1015 | 920 | 0 | 3 |
T6 | 579190 | 579030 | 0 | 3 |
T7 | 284840 | 284768 | 0 | 3 |
T8 | 0 | 0 | 0 | 3 |
T11 | 3741 | 3102 | 0 | 3 |
T12 | 1523 | 1293 | 0 | 3 |
T19 | 3310 | 3133 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 381473027 | 380654093 | 0 | 0 |
gen_flops.OutputDelay_A | 381473027 | 380621966 | 0 | 2724 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380654093 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 1015 | 923 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380621966 | 0 | 2724 |
T1 | 2120 | 2038 | 0 | 3 |
T2 | 6410 | 5793 | 0 | 3 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169295 | 0 | 3 |
T5 | 1015 | 920 | 0 | 3 |
T6 | 579190 | 579030 | 0 | 3 |
T7 | 284840 | 284768 | 0 | 3 |
T8 | 0 | 0 | 0 | 3 |
T11 | 3741 | 3102 | 0 | 3 |
T12 | 1523 | 1293 | 0 | 3 |
T19 | 3310 | 3133 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 381473027 | 380654093 | 0 | 0 |
gen_flops.OutputDelay_A | 381473027 | 380621966 | 0 | 2724 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380654093 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 1015 | 923 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380621966 | 0 | 2724 |
T1 | 2120 | 2038 | 0 | 3 |
T2 | 6410 | 5793 | 0 | 3 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169295 | 0 | 3 |
T5 | 1015 | 920 | 0 | 3 |
T6 | 579190 | 579030 | 0 | 3 |
T7 | 284840 | 284768 | 0 | 3 |
T8 | 0 | 0 | 0 | 3 |
T11 | 3741 | 3102 | 0 | 3 |
T12 | 1523 | 1293 | 0 | 3 |
T19 | 3310 | 3133 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 381473027 | 380654093 | 0 | 0 |
gen_flops.OutputDelay_A | 381473027 | 380621966 | 0 | 2724 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380654093 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 1015 | 923 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380621966 | 0 | 2724 |
T1 | 2120 | 2038 | 0 | 3 |
T2 | 6410 | 5793 | 0 | 3 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169295 | 0 | 3 |
T5 | 1015 | 920 | 0 | 3 |
T6 | 579190 | 579030 | 0 | 3 |
T7 | 284840 | 284768 | 0 | 3 |
T8 | 0 | 0 | 0 | 3 |
T11 | 3741 | 3102 | 0 | 3 |
T12 | 1523 | 1293 | 0 | 3 |
T19 | 3310 | 3133 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 381473027 | 380654093 | 0 | 0 |
gen_flops.OutputDelay_A | 381473027 | 380621966 | 0 | 2724 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380654093 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 1015 | 923 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380621966 | 0 | 2724 |
T1 | 2120 | 2038 | 0 | 3 |
T2 | 6410 | 5793 | 0 | 3 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169295 | 0 | 3 |
T5 | 1015 | 920 | 0 | 3 |
T6 | 579190 | 579030 | 0 | 3 |
T7 | 284840 | 284768 | 0 | 3 |
T8 | 0 | 0 | 0 | 3 |
T11 | 3741 | 3102 | 0 | 3 |
T12 | 1523 | 1293 | 0 | 3 |
T19 | 3310 | 3133 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 381473027 | 380654093 | 0 | 0 |
gen_flops.OutputDelay_A | 381473027 | 380621966 | 0 | 2724 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380654093 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 1015 | 923 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381473027 | 380621966 | 0 | 2724 |
T1 | 2120 | 2038 | 0 | 3 |
T2 | 6410 | 5793 | 0 | 3 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169295 | 0 | 3 |
T5 | 1015 | 920 | 0 | 3 |
T6 | 579190 | 579030 | 0 | 3 |
T7 | 284840 | 284768 | 0 | 3 |
T8 | 0 | 0 | 0 | 3 |
T11 | 3741 | 3102 | 0 | 3 |
T12 | 1523 | 1293 | 0 | 3 |
T19 | 3310 | 3133 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 381472892 | 380653958 | 0 | 0 |
gen_no_flops.OutputDelay_A | 381472892 | 380653958 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381472892 | 380653958 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 1015 | 923 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381472892 | 380653958 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 1015 | 923 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 381448470 | 380629536 | 0 | 0 |
gen_flops.OutputDelay_A | 381448470 | 380597559 | 0 | 2574 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381448470 | 380629536 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 483 | 391 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381448470 | 380597559 | 0 | 2574 |
T1 | 2120 | 2038 | 0 | 3 |
T2 | 6410 | 5793 | 0 | 3 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169295 | 0 | 3 |
T5 | 483 | 391 | 0 | 0 |
T6 | 579190 | 579030 | 0 | 3 |
T7 | 284840 | 284768 | 0 | 3 |
T8 | 0 | 0 | 0 | 3 |
T11 | 3741 | 3102 | 0 | 3 |
T12 | 1523 | 1293 | 0 | 3 |
T19 | 3310 | 3133 | 0 | 3 |
T20 | 0 | 0 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 381472892 | 380653958 | 0 | 0 |
gen_no_flops.OutputDelay_A | 381472892 | 380653958 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381472892 | 380653958 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 1015 | 923 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381472892 | 380653958 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 1015 | 923 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1044 | 1044 | 0 | 0 |
OutputsKnown_A | 381472892 | 380653958 | 0 | 0 |
gen_flops.OutputDelay_A | 381472892 | 380621846 | 0 | 2724 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1044 | 1044 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381472892 | 380653958 | 0 | 0 |
T1 | 2120 | 2041 | 0 | 0 |
T2 | 6410 | 5814 | 0 | 0 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169301 | 0 | 0 |
T5 | 1015 | 923 | 0 | 0 |
T6 | 579190 | 579036 | 0 | 0 |
T7 | 284840 | 284771 | 0 | 0 |
T11 | 3741 | 3129 | 0 | 0 |
T12 | 1523 | 1302 | 0 | 0 |
T19 | 3310 | 3139 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 381472892 | 380621846 | 0 | 2724 |
T1 | 2120 | 2038 | 0 | 3 |
T2 | 6410 | 5793 | 0 | 3 |
T3 | 370 | 274 | 0 | 0 |
T4 | 169445 | 169295 | 0 | 3 |
T5 | 1015 | 920 | 0 | 3 |
T6 | 579190 | 579030 | 0 | 3 |
T7 | 284840 | 284768 | 0 | 3 |
T8 | 0 | 0 | 0 | 3 |
T11 | 3741 | 3102 | 0 | 3 |
T12 | 1523 | 1293 | 0 | 3 |
T19 | 3310 | 3133 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |