Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25421658	1		T1	101502		T2	2522		T3	97501
full_word	7555566	1		T1	22658		T2	2075		T3	11343

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32976904	1		T1	124160		T2	4597		T3	108844
auto[TlIntgErrCmd]	106	1		T64	3		T102	3		T103	8
auto[TlIntgErrData]	111	1		T64	7		T102	3		T103	6
auto[TlIntgErrBoth]	103	1		T64	10		T102	4		T103	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28631294	1		T1	106308		T2	3687		T3	97095
auto[1]	4345930	1		T1	17852		T2	910		T3	11749

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24802352	1		T1	100337		T2	1971		T3	96256
auto[TlIntgErrNone]	partial	auto[1]	619016	1		T1	1165		T2	551		T3	1245
auto[TlIntgErrNone]	full_word	auto[0]	3828798	1		T1	5971		T2	1716		T3	839
auto[TlIntgErrNone]	full_word	auto[1]	3726738	1		T1	16687		T2	359		T3	10504
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T64	1		T102	2		T103	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T64	1		T102	1		T103	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T386	1		T387	1		T287	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T64	1		T103	2		T229	1
auto[TlIntgErrData]	partial	auto[0]	55	1		T64	3		T102	2		T103	3
auto[TlIntgErrData]	partial	auto[1]	45	1		T64	3		T102	1		T103	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T284	1		T386	1		T390	1
auto[TlIntgErrData]	full_word	auto[1]	8	1		T64	1		T103	1		T280	3
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T64	4		T102	2		T103	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1		T64	6		T103	3		T229	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T102	1		T391	1		T287	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T102	1		T103	1		T392	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21869	1		T101	721		T64	16		T102	7
full_word	3943675	1		T2	16188		T5	15218		T21	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3965251	1		T2	16188		T5	15218		T21	4
auto[TlIntgErrCmd]	85	1		T64	7		T102	5		T103	3
auto[TlIntgErrData]	108	1		T64	5		T102	2		T103	10
auto[TlIntgErrBoth]	100	1		T64	5		T102	3		T103	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3938782	1		T2	16188		T5	15218		T21	4
auto[1]	26762	1		T101	891		T64	8		T102	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1529	1		T101	59		T227	43		T228	54
auto[TlIntgErrNone]	partial	auto[1]	20086	1		T101	662		T227	530		T228	628
auto[TlIntgErrNone]	full_word	auto[0]	3937130	1		T2	16188		T5	15218		T21	4
auto[TlIntgErrNone]	full_word	auto[1]	6506	1		T101	229		T227	185		T228	213
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T64	4		T284	3		T280	4
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T64	2		T102	3		T103	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T102	1		T391	1		T390	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T64	1		T102	1		T103	1
auto[TlIntgErrData]	partial	auto[0]	51	1		T64	4		T102	2		T103	6
auto[TlIntgErrData]	partial	auto[1]	46	1		T64	1		T103	3		T229	4
auto[TlIntgErrData]	full_word	auto[0]	8	1		T393	1		T386	1		T389	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T103	1		T284	1		T280	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1		T64	1		T102	1		T103	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T64	4		T102	1		T103	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T102	1		T103	1		T229	1
auto[TlIntgErrBoth]	full_word	auto[1]	12	1		T103	1		T240	2		T284	1