Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T21

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1614364576	1610767212	0	0
CheckNGreaterZero_A	4160	4160	0	0
GntImpliesReady_A	1614364576	400579195	0	0
GntImpliesValid_A	1614364576	400579195	0	0
GrantKnown_A	1614364576	1610767212	0	0
IdxKnown_A	1614364576	1610767212	0	0
IndexIsCorrect_A	1614364576	400579195	0	0
NoReadyValidNoGrant_A	1614364576	171827493	0	0
Priority_A	1614364576	423514170	0	0
ReadyAndValidImplyGrant_A	1614364576	400579195	0	0
ReqAndReadyImplyGrant_A	1614364576	400579195	0	0
ReqImpliesValid_A	1614364576	423514170	0	0
ValidKnown_A	1614364576	1610767212	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	1610767212	0	0
T1	452120	452080	0	0
T2	2260188	2259560	0	0
T3	875784	875560	0	0
T4	605476	605136	0	0
T5	260288	259900	0	0
T17	1202136	1147952	0	0
T18	184776	173648	0	0
T19	6472	6244	0	0
T20	14876	14628	0	0
T21	9592	9040	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4160	4160	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	400579195	0	0
T1	452120	1558650	0	0
T2	2260188	35048	0	0
T3	875784	388504	0	0
T4	605476	30366	0	0
T5	260288	41750	0	0
T6	0	17250	0	0
T10	0	255794	0	0
T17	1202136	256604	0	0
T18	184776	56656	0	0
T19	6472	64	0	0
T20	14876	2590	0	0
T21	9592	348	0	0
T25	0	6	0	0
T37	0	839698	0	0
T59	0	207468	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	400579195	0	0
T1	452120	1558650	0	0
T2	2260188	35048	0	0
T3	875784	388504	0	0
T4	605476	30366	0	0
T5	260288	41750	0	0
T6	0	17250	0	0
T10	0	255794	0	0
T17	1202136	256604	0	0
T18	184776	56656	0	0
T19	6472	64	0	0
T20	14876	2590	0	0
T21	9592	348	0	0
T25	0	6	0	0
T37	0	839698	0	0
T59	0	207468	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	1610767212	0	0
T1	452120	452080	0	0
T2	2260188	2259560	0	0
T3	875784	875560	0	0
T4	605476	605136	0	0
T5	260288	259900	0	0
T17	1202136	1147952	0	0
T18	184776	173648	0	0
T19	6472	6244	0	0
T20	14876	14628	0	0
T21	9592	9040	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	1610767212	0	0
T1	452120	452080	0	0
T2	2260188	2259560	0	0
T3	875784	875560	0	0
T4	605476	605136	0	0
T5	260288	259900	0	0
T17	1202136	1147952	0	0
T18	184776	173648	0	0
T19	6472	6244	0	0
T20	14876	14628	0	0
T21	9592	9040	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	400579195	0	0
T1	452120	1558650	0	0
T2	2260188	35048	0	0
T3	875784	388504	0	0
T4	605476	30366	0	0
T5	260288	41750	0	0
T6	0	17250	0	0
T10	0	255794	0	0
T17	1202136	256604	0	0
T18	184776	56656	0	0
T19	6472	64	0	0
T20	14876	2590	0	0
T21	9592	348	0	0
T25	0	6	0	0
T37	0	839698	0	0
T59	0	207468	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	171827493	0	0
T1	452120	3902	0	0
T2	2260188	1203344	0	0
T3	875784	256	0	0
T4	605476	6784	0	0
T5	260288	120068	0	0
T6	0	635162	0	0
T10	0	1048576	0	0
T17	1202136	68096	0	0
T18	184776	13288	0	0
T19	6472	256	0	0
T20	14876	256	0	0
T21	9592	696	0	0
T25	0	18	0	0
T35	0	166576	0	0
T37	0	1049068	0	0
T53	0	517932	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	423514170	0	0
T1	452120	1558650	0	0
T2	2260188	555154	0	0
T3	875784	388504	0	0
T4	605476	30366	0	0
T5	260288	43772	0	0
T6	0	254432	0	0
T10	0	255794	0	0
T17	1202136	256604	0	0
T18	184776	56656	0	0
T19	6472	64	0	0
T20	14876	2590	0	0
T21	9592	348	0	0
T25	0	6	0	0
T37	0	839698	0	0
T59	0	207468	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	400579195	0	0
T1	452120	1558650	0	0
T2	2260188	35048	0	0
T3	875784	388504	0	0
T4	605476	30366	0	0
T5	260288	41750	0	0
T6	0	17250	0	0
T10	0	255794	0	0
T17	1202136	256604	0	0
T18	184776	56656	0	0
T19	6472	64	0	0
T20	14876	2590	0	0
T21	9592	348	0	0
T25	0	6	0	0
T37	0	839698	0	0
T59	0	207468	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	400579195	0	0
T1	452120	1558650	0	0
T2	2260188	35048	0	0
T3	875784	388504	0	0
T4	605476	30366	0	0
T5	260288	41750	0	0
T6	0	17250	0	0
T10	0	255794	0	0
T17	1202136	256604	0	0
T18	184776	56656	0	0
T19	6472	64	0	0
T20	14876	2590	0	0
T21	9592	348	0	0
T25	0	6	0	0
T37	0	839698	0	0
T59	0	207468	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	423514170	0	0
T1	452120	1558650	0	0
T2	2260188	555154	0	0
T3	875784	388504	0	0
T4	605476	30366	0	0
T5	260288	43772	0	0
T6	0	254432	0	0
T10	0	255794	0	0
T17	1202136	256604	0	0
T18	184776	56656	0	0
T19	6472	64	0	0
T20	14876	2590	0	0
T21	9592	348	0	0
T25	0	6	0	0
T37	0	839698	0	0
T59	0	207468	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1614364576	1610767212	0	0
T1	452120	452080	0	0
T2	2260188	2259560	0	0
T3	875784	875560	0	0
T4	605476	605136	0	0
T5	260288	259900	0	0
T17	1202136	1147952	0	0
T18	184776	173648	0	0
T19	6472	6244	0	0
T20	14876	14628	0	0
T21	9592	9040	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403591144	402691803	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	403591144	101899884	0	0
GntImpliesValid_A	403591144	101899884	0	0
GrantKnown_A	403591144	402691803	0	0
IdxKnown_A	403591144	402691803	0	0
IndexIsCorrect_A	403591144	101899884	0	0
NoReadyValidNoGrant_A	403591144	44648907	0	0
Priority_A	403591144	107604427	0	0
ReadyAndValidImplyGrant_A	403591144	101899884	0	0
ReqAndReadyImplyGrant_A	403591144	101899884	0	0
ReqImpliesValid_A	403591144	107604427	0	0
ValidKnown_A	403591144	402691803	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	101899884	0	0
T1	113030	33055	0	0
T2	565047	8718	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	9549	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	101899884	0	0
T1	113030	33055	0	0
T2	565047	8718	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	9549	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	101899884	0	0
T1	113030	33055	0	0
T2	565047	8718	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	9549	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	44648907	0	0
T1	113030	306	0	0
T2	565047	320121	0	0
T3	218946	128	0	0
T4	151369	3392	0	0
T5	65072	27950	0	0
T17	300534	34048	0	0
T18	46194	6644	0	0
T19	1618	128	0	0
T20	3719	128	0	0
T21	2398	325	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	107604427	0	0
T1	113030	33055	0	0
T2	565047	106151	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	10234	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	101899884	0	0
T1	113030	33055	0	0
T2	565047	8718	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	9549	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	101899884	0	0
T1	113030	33055	0	0
T2	565047	8718	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	9549	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	107604427	0	0
T1	113030	33055	0	0
T2	565047	106151	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	10234	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T21
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403591144	402691803	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	403591144	101899809	0	0
GntImpliesValid_A	403591144	101899809	0	0
GrantKnown_A	403591144	402691803	0	0
IdxKnown_A	403591144	402691803	0	0
IndexIsCorrect_A	403591144	101899809	0	0
NoReadyValidNoGrant_A	403591144	44648908	0	0
Priority_A	403591144	107604351	0	0
ReadyAndValidImplyGrant_A	403591144	101899809	0	0
ReqAndReadyImplyGrant_A	403591144	101899809	0	0
ReqImpliesValid_A	403591144	107604351	0	0
ValidKnown_A	403591144	402691803	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	101899809	0	0
T1	113030	33055	0	0
T2	565047	8718	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	9549	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	101899809	0	0
T1	113030	33055	0	0
T2	565047	8718	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	9549	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	101899809	0	0
T1	113030	33055	0	0
T2	565047	8718	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	9549	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	44648908	0	0
T1	113030	306	0	0
T2	565047	320121	0	0
T3	218946	128	0	0
T4	151369	3392	0	0
T5	65072	27950	0	0
T17	300534	34048	0	0
T18	46194	6644	0	0
T19	1618	128	0	0
T20	3719	128	0	0
T21	2398	325	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	107604351	0	0
T1	113030	33055	0	0
T2	565047	106151	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	10234	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	101899809	0	0
T1	113030	33055	0	0
T2	565047	8718	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	9549	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	101899809	0	0
T1	113030	33055	0	0
T2	565047	8718	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	9549	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	107604351	0	0
T1	113030	33055	0	0
T2	565047	106151	0	0
T3	218946	98252	0	0
T4	151369	15183	0	0
T5	65072	10234	0	0
T17	300534	128302	0	0
T18	46194	28328	0	0
T19	1618	32	0	0
T20	3719	1295	0	0
T21	2398	159	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T5,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T3,T5
1	1	Covered	T2,T5,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T21
1	1	Covered	T1,T3,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403591144	402691803	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	403591144	98389751	0	0
GntImpliesValid_A	403591144	98389751	0	0
GrantKnown_A	403591144	402691803	0	0
IdxKnown_A	403591144	402691803	0	0
IndexIsCorrect_A	403591144	98389751	0	0
NoReadyValidNoGrant_A	403591144	41264839	0	0
Priority_A	403591144	104152696	0	0
ReadyAndValidImplyGrant_A	403591144	98389751	0	0
ReqAndReadyImplyGrant_A	403591144	98389751	0	0
ReqImpliesValid_A	403591144	104152696	0	0
ValidKnown_A	403591144	402691803	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	98389751	0	0
T1	113030	746270	0	0
T2	565047	8806	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11326	0	0
T6	0	8625	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	98389751	0	0
T1	113030	746270	0	0
T2	565047	8806	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11326	0	0
T6	0	8625	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	98389751	0	0
T1	113030	746270	0	0
T2	565047	8806	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11326	0	0
T6	0	8625	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	41264839	0	0
T1	113030	1645	0	0
T2	565047	281551	0	0
T3	218946	0	0	0
T4	151369	0	0	0
T5	65072	32084	0	0
T6	0	317581	0	0
T10	0	524288	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	23	0	0
T25	0	9	0	0
T35	0	83288	0	0
T37	0	524534	0	0
T53	0	258966	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	104152696	0	0
T1	113030	746270	0	0
T2	565047	171426	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11652	0	0
T6	0	127216	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	98389751	0	0
T1	113030	746270	0	0
T2	565047	8806	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11326	0	0
T6	0	8625	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	98389751	0	0
T1	113030	746270	0	0
T2	565047	8806	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11326	0	0
T6	0	8625	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	104152696	0	0
T1	113030	746270	0	0
T2	565047	171426	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11652	0	0
T6	0	127216	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T5,T21

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T5,T21
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T3,T5
1	1	Covered	T2,T5,T21

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T21
1	1	Covered	T1,T3,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T21

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T5,T21

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403591144	402691803	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	403591144	98389751	0	0
GntImpliesValid_A	403591144	98389751	0	0
GrantKnown_A	403591144	402691803	0	0
IdxKnown_A	403591144	402691803	0	0
IndexIsCorrect_A	403591144	98389751	0	0
NoReadyValidNoGrant_A	403591144	41264839	0	0
Priority_A	403591144	104152696	0	0
ReadyAndValidImplyGrant_A	403591144	98389751	0	0
ReqAndReadyImplyGrant_A	403591144	98389751	0	0
ReqImpliesValid_A	403591144	104152696	0	0
ValidKnown_A	403591144	402691803	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	98389751	0	0
T1	113030	746270	0	0
T2	565047	8806	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11326	0	0
T6	0	8625	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	98389751	0	0
T1	113030	746270	0	0
T2	565047	8806	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11326	0	0
T6	0	8625	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	98389751	0	0
T1	113030	746270	0	0
T2	565047	8806	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11326	0	0
T6	0	8625	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	41264839	0	0
T1	113030	1645	0	0
T2	565047	281551	0	0
T3	218946	0	0	0
T4	151369	0	0	0
T5	65072	32084	0	0
T6	0	317581	0	0
T10	0	524288	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	23	0	0
T25	0	9	0	0
T35	0	83288	0	0
T37	0	524534	0	0
T53	0	258966	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	104152696	0	0
T1	113030	746270	0	0
T2	565047	171426	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11652	0	0
T6	0	127216	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	98389751	0	0
T1	113030	746270	0	0
T2	565047	8806	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11326	0	0
T6	0	8625	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	98389751	0	0
T1	113030	746270	0	0
T2	565047	8806	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11326	0	0
T6	0	8625	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	104152696	0	0
T1	113030	746270	0	0
T2	565047	171426	0	0
T3	218946	96000	0	0
T4	151369	0	0	0
T5	65072	11652	0	0
T6	0	127216	0	0
T10	0	127897	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	3	0	0
T37	0	419849	0	0
T59	0	103734	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0