Unified Coverage Report :: Module :: flash_phy_rd

Module : flash_phy_rd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.81	100.00	91.25			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd	97.54	100.00	90.15			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd	97.76	100.00	91.03			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.54	100.00	90.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.33	97.64	93.07	100.00		99.37	96.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.76	100.00	91.03			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.39	97.64	93.39	100.00		99.37	96.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
gen_rd.gen_bus_words_intg[0].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_bus_intg	100.00	100.00
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg	100.00	100.00
u_addr_xor_storage	96.53	100.00	86.11			100.00	100.00
u_bus_inv_data_intg	0.00	0.00
u_dec	100.00	100.00	100.00
u_intg_buf	100.00	100.00
u_mask_storage	93.75	100.00	80.56			94.44	100.00
u_plain_enc	100.00	100.00
u_prim_buf_data_xor_out	100.00	100.00
u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
u_rd_storage	97.44	100.00	87.18	100.00		100.00	100.00
u_rsp_order_fifo	97.44	100.00	87.18	100.00		100.00	100.00
u_valid_random	94.17	92.31	97.69			100.00	86.67

Line Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Module : flash_phy_rd

	Total	Covered	Percent
Conditions	457	417	91.25
Logical	457	417	91.25
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-790	91.44
790-794	84.62

---

Branch Coverage for Module : flash_phy_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T21,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T23,T57,T27
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T21,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	807182288	1552660	0	0
ExclusiveOps_A	807182288	805383606	0	0
ExclusiveProgHazard_A	807182288	805383606	0	0
ExclusiveState_A	807182288	805383606	0	0
ForwardCheck_A	807182288	3609176	0	0
IdleCheck_A	807182288	98661425	0	0
MaxBufs_A	2080	2080	0	0
OneHotAlloc_A	807182288	805383606	0	0
OneHotMatch_A	807182288	805383606	0	0
OneHotRspMatch_A	807182288	805383606	0	0
OneHotUpdate_A	807182288	805383606	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807182288	1552660	0	0
T1	226060	593	0	0
T2	1130094	483	0	0
T3	437892	0	0	0
T4	302738	768	0	0
T5	130144	1618	0	0
T6	0	498	0	0
T11	0	4	0	0
T17	601068	2304	0	0
T18	92388	420	0	0
T19	3236	0	0	0
T20	7438	0	0	0
T21	4796	22	0	0
T22	0	27	0	0
T25	0	43	0	0
T35	0	1916	0	0
T37	0	76	0	0
T45	0	54	0	0
T83	0	73	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807182288	805383606	0	0
T1	226060	226040	0	0
T2	1130094	1129780	0	0
T3	437892	437780	0	0
T4	302738	302568	0	0
T5	130144	129950	0	0
T17	601068	573976	0	0
T18	92388	86824	0	0
T19	3236	3122	0	0
T20	7438	7314	0	0
T21	4796	4520	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807182288	805383606	0	0
T1	226060	226040	0	0
T2	1130094	1129780	0	0
T3	437892	437780	0	0
T4	302738	302568	0	0
T5	130144	129950	0	0
T17	601068	573976	0	0
T18	92388	86824	0	0
T19	3236	3122	0	0
T20	7438	7314	0	0
T21	4796	4520	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807182288	805383606	0	0
T1	226060	226040	0	0
T2	1130094	1129780	0	0
T3	437892	437780	0	0
T4	302738	302568	0	0
T5	130144	129950	0	0
T17	601068	573976	0	0
T18	92388	86824	0	0
T19	3236	3122	0	0
T20	7438	7314	0	0
T21	4796	4520	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807182288	3609176	0	0
T1	226060	615	0	0
T2	1130094	17004	0	0
T3	437892	0	0	0
T4	302738	288	0	0
T5	130144	0	0	0
T6	0	17824	0	0
T17	601068	0	0	0
T18	92388	0	0	0
T19	3236	0	0	0
T20	7438	0	0	0
T21	4796	19	0	0
T22	0	109	0	0
T23	0	23	0	0
T31	0	288	0	0
T37	0	144	0	0
T45	0	68	0	0
T53	0	16515	0	0
T83	0	73	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807182288	98661425	0	0
T1	226060	1951	0	0
T2	1130094	869605	0	0
T3	437892	128	0	0
T4	302738	3392	0	0
T5	130144	69014	0	0
T6	0	439875	0	0
T10	0	524288	0	0
T17	601068	34048	0	0
T18	92388	6644	0	0
T19	3236	128	0	0
T20	7438	128	0	0
T21	4796	348	0	0
T25	0	9	0	0
T35	0	102588	0	0
T37	0	524534	0	0
T53	0	445077	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2080	2080	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807182288	805383606	0	0
T1	226060	226040	0	0
T2	1130094	1129780	0	0
T3	437892	437780	0	0
T4	302738	302568	0	0
T5	130144	129950	0	0
T17	601068	573976	0	0
T18	92388	86824	0	0
T19	3236	3122	0	0
T20	7438	7314	0	0
T21	4796	4520	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807182288	805383606	0	0
T1	226060	226040	0	0
T2	1130094	1129780	0	0
T3	437892	437780	0	0
T4	302738	302568	0	0
T5	130144	129950	0	0
T17	601068	573976	0	0
T18	92388	86824	0	0
T19	3236	3122	0	0
T20	7438	7314	0	0
T21	4796	4520	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807182288	805383606	0	0
T1	226060	226040	0	0
T2	1130094	1129780	0	0
T3	437892	437780	0	0
T4	302738	302568	0	0
T5	130144	129950	0	0
T17	601068	573976	0	0
T18	92388	86824	0	0
T19	3236	3122	0	0
T20	7438	7314	0	0
T21	4796	4520	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	807182288	805383606	0	0
T1	226060	226040	0	0
T2	1130094	1129780	0	0
T3	437892	437780	0	0
T4	302738	302568	0	0
T5	130144	129950	0	0
T17	601068	573976	0	0
T18	92388	86824	0	0
T19	3236	3122	0	0
T20	7438	7314	0	0
T21	4796	4520	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Covered	Percent
Conditions	457	412	90.15
Logical	457	412	90.15
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-790	90.60
790-794	70.00

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T35,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T10,T25
0	1	Covered	T57,T27,T62
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T21
0	1	Covered	T5,T10,T25
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T21
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T21

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T21
0	1	Covered	T5,T10,T25
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T138,T140
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T10,T25
0	0	1	Covered	T5,T10,T25
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	403591144	735776	0	0
ExclusiveOps_A	403591144	402691803	0	0
ExclusiveProgHazard_A	403591144	402691803	0	0
ExclusiveState_A	403591144	402691803	0	0
ForwardCheck_A	403591144	1682167	0	0
IdleCheck_A	403591144	47679659	0	0
MaxBufs_A	1040	1040	0	0
OneHotAlloc_A	403591144	402691803	0	0
OneHotMatch_A	403591144	402691803	0	0
OneHotRspMatch_A	403591144	402691803	0	0
OneHotUpdate_A	403591144	402691803	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	735776	0	0
T1	113030	541	0	0
T2	565047	5	0	0
T3	218946	0	0	0
T4	151369	0	0	0
T5	65072	1137	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	7	0	0
T22	0	27	0	0
T25	0	1	0	0
T35	0	1916	0	0
T37	0	76	0	0
T45	0	54	0	0
T83	0	73	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	1682167	0	0
T1	113030	552	0	0
T2	565047	8801	0	0
T3	218946	0	0	0
T4	151369	0	0	0
T5	65072	0	0	0
T6	0	8625	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	8	0	0
T22	0	32	0	0
T23	0	6	0	0
T37	0	85	0	0
T45	0	68	0	0
T53	0	8727	0	0
T83	0	73	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	47679659	0	0
T1	113030	1645	0	0
T2	565047	448856	0	0
T3	218946	0	0	0
T4	151369	0	0	0
T5	65072	36307	0	0
T6	0	439875	0	0
T10	0	524288	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	23	0	0
T25	0	9	0	0
T35	0	102588	0	0
T37	0	524534	0	0
T53	0	445077	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
TOTAL		133	133	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	186	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	229	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
ALWAYS	257	4	4	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	331	1	1	100.00
ALWAYS	360	12	12	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	497	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
ALWAYS	600	6	6	100.00
CONT_ASSIGN	610	1	1	100.00
CONT_ASSIGN	614	1	1	100.00
CONT_ASSIGN	617	1	1	100.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	654	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
CONT_ASSIGN	664	1	1	100.00
ALWAYS	670	8	8	100.00
CONT_ASSIGN	683	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	745	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	775	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	797	1	1	100.00
CONT_ASSIGN	800	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
140	4	4
141	4	4
146	4	4
152	1	1
154	3	3
186	1	1
193	4	4
194	4	4
196	4	4
212	4	4
218	4	4
222	4	4
229	1	1
232	1	1
257	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
291	1	1
292	1	1
302	1	1
305	1	1
308	1	1
326	1	1
331	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
			MISSING_ELSE
377	1	1
382	1	1
393	1	1
399	1	1
407	1	1
428	1	1
432	1	1
442	1	1
445	1	1
451	1	1
456	1	1
459	1	1
491	1	1
494	1	1
497	1	1
501	1	1
503	1	1
504	1	1
505	1	1
513	1	1
521	1	1
523	1	1
597	1	1
598	1	1
600	1	1
601	1	1
602	1	1
603	1	1
604	1	1
605	1	1
			MISSING_ELSE
610	1	1
614	1	1
617	1	1
624	1	1
628	1	1
636	1	1
654	1	1
659	1	1
664	4	4
670	1	1
671	1	1
672	1	1
673	1	1
674	1	1
675	1	1
676	1	1
677	1	1
			MISSING_ELSE
683	1	1
704	1	1
724	1	1
736	1	1
738	1	1
744	1	1
745	1	1
747	1	1
751	1	1
762	1	1
775	1	1
787	1	1
790	1	1
794	1	1
797	1	1
800	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Covered	Percent
Conditions	457	416	91.03
Logical	457	416	91.03
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
140-790	91.22
790-794	84.62

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Line No.	Total	Covered	Percent
Branches		43	43	100.00
TERNARY	186	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	302	2	2	100.00
TERNARY	451	2	2	100.00
TERNARY	513	3	3	100.00
TERNARY	624	3	3	100.00
TERNARY	628	3	3	100.00
TERNARY	654	3	3	100.00
TERNARY	683	2	2	100.00
TERNARY	736	2	2	100.00
TERNARY	747	2	2	100.00
TERNARY	775	2	2	100.00
TERNARY	167	2	2	100.00
IF	257	3	3	100.00
IF	360	4	4	100.00
IF	600	4	4	100.00
IF	674	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	186	((|buf_invalid_alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	232	(no_match) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	302	((|alloc)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	451	((data_err | ecc_single_err_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T21,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	(hint_descram) ? 
-2-:	513	(hint_dropmsk) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T23,T57,T27
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	624	(forward) ? 
-2-:	624	(hint_descram) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	628	(forward) ? 
-2-:	628	((~hint_forward)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	654	(forward) ? 
-2-:	654	(((~hint_forward) & fifo_data_ready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	683	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	736	(data_err_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T21,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	747	((|buf_rsp_match)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	775	(rsp_fifo_rdata.intg_ecc_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(((|buf_invalid_alloc) | all_buf_dependency)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	257	if ((!rst_ni))
-2-:	259	if (idle_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	360	if ((!rst_ni))
-2-:	364	if (rd_start)
-3-:	371	if (rd_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	600	if ((!rst_ni))
-2-:	602	if (calc_req_start)
-3-:	604	if (calc_req_done)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	674	if (buf_rsp_match[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferMatchEcc_A	403591144	816884	0	0
ExclusiveOps_A	403591144	402691803	0	0
ExclusiveProgHazard_A	403591144	402691803	0	0
ExclusiveState_A	403591144	402691803	0	0
ForwardCheck_A	403591144	1927009	0	0
IdleCheck_A	403591144	50981766	0	0
MaxBufs_A	1040	1040	0	0
OneHotAlloc_A	403591144	402691803	0	0
OneHotMatch_A	403591144	402691803	0	0
OneHotRspMatch_A	403591144	402691803	0	0
OneHotUpdate_A	403591144	402691803	0	0

BufferMatchEcc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	816884	0	0
T1	113030	52	0	0
T2	565047	478	0	0
T3	218946	0	0	0
T4	151369	768	0	0
T5	65072	481	0	0
T6	0	498	0	0
T11	0	4	0	0
T17	300534	2304	0	0
T18	46194	420	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	15	0	0
T25	0	42	0	0

ExclusiveOps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

ExclusiveProgHazard_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

ExclusiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

ForwardCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	1927009	0	0
T1	113030	63	0	0
T2	565047	8203	0	0
T3	218946	0	0	0
T4	151369	288	0	0
T5	65072	0	0	0
T6	0	9199	0	0
T17	300534	0	0	0
T18	46194	0	0	0
T19	1618	0	0	0
T20	3719	0	0	0
T21	2398	11	0	0
T22	0	77	0	0
T23	0	17	0	0
T31	0	288	0	0
T37	0	59	0	0
T53	0	7788	0	0

IdleCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	50981766	0	0
T1	113030	306	0	0
T2	565047	420749	0	0
T3	218946	128	0	0
T4	151369	3392	0	0
T5	65072	32707	0	0
T17	300534	34048	0	0
T18	46194	6644	0	0
T19	1618	128	0	0
T20	3719	128	0	0
T21	2398	325	0	0

MaxBufs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

OneHotAlloc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

OneHotMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

OneHotRspMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0

OneHotUpdate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403591144	402691803	0	0
T1	113030	113020	0	0
T2	565047	564890	0	0
T3	218946	218890	0	0
T4	151369	151284	0	0
T5	65072	64975	0	0
T17	300534	286988	0	0
T18	46194	43412	0	0
T19	1618	1561	0	0
T20	3719	3657	0	0
T21	2398	2260	0	0