Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22257265	1		T1	4857		T2	120		T3	4851
full_word	7639008	1		T1	9581		T2	152		T3	1974

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29895963	1		T1	14438		T2	272		T3	6825
auto[TlIntgErrCmd]	116	1		T62	7		T63	5		T233	11
auto[TlIntgErrData]	108	1		T62	8		T63	4		T233	5
auto[TlIntgErrBoth]	86	1		T62	5		T63	1		T233	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	25468662	1		T1	8896		T2	125		T3	4703
auto[1]	4427611	1		T1	5542		T2	147		T3	2122

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21562347	1		T1	4625		T2	111		T3	4595
auto[TlIntgErrNone]	partial	auto[1]	694640	1		T1	232		T2	9		T3	256
auto[TlIntgErrNone]	full_word	auto[0]	3906170	1		T1	4271		T2	14		T3	108
auto[TlIntgErrNone]	full_word	auto[1]	3732806	1		T1	5310		T2	138		T3	1866
auto[TlIntgErrCmd]	partial	auto[0]	47	1		T62	3		T63	3		T233	3
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T62	4		T63	2		T233	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T233	2		T285	1		T307	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T233	1		T347	1		T285	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T62	5		T63	2		T233	1
auto[TlIntgErrData]	partial	auto[1]	50	1		T62	3		T63	1		T233	4
auto[TlIntgErrData]	full_word	auto[0]	4	1		T353	1		T344	1		T349	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T63	1		T279	1		T285	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T62	4		T63	1		T233	3
auto[TlIntgErrBoth]	partial	auto[1]	35	1		T62	1		T233	1		T279	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T347	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T347	1		T353	1		T348	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22609	1		T62	16		T94	958		T63	7
full_word	3980791	1		T18	10		T4	161		T5	16326

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4003112	1		T18	10		T4	161		T5	16326
auto[TlIntgErrCmd]	85	1		T62	6		T63	4		T233	7
auto[TlIntgErrData]	111	1		T62	9		T63	4		T233	7
auto[TlIntgErrBoth]	92	1		T62	3		T63	2		T233	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3973979	1		T18	10		T4	161		T5	16326
auto[1]	29421	1		T62	6		T94	1311		T63	2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1537	1		T94	95		T231	46		T95	4
auto[TlIntgErrNone]	partial	auto[1]	20807	1		T94	863		T231	1030		T95	28
auto[TlIntgErrNone]	full_word	auto[0]	3972324	1		T18	10		T4	161		T5	16326
auto[TlIntgErrNone]	full_word	auto[1]	8444	1		T94	448		T231	404		T95	7
auto[TlIntgErrCmd]	partial	auto[0]	24	1		T62	1		T63	2		T233	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T62	3		T63	2		T233	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T62	2		T352	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T349	1		T351	1		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1		T62	7		T63	2		T233	5
auto[TlIntgErrData]	partial	auto[1]	48	1		T62	2		T233	2		T279	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T63	2		T279	1		T285	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T347	1		T345	1		T354	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1		T62	2		T63	1		T233	2
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T62	1		T233	1		T279	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T63	1		T348	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T233	1		T279	1		T348	1