Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T15
1	0	Covered	T18,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T18,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T18,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T15
1	1	Covered	T18,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T4,T5
1	1	Covered	T1,T2,T15

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T15

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T18,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T18,T4,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1515211272	1511820768	0	0
CheckNGreaterZero_A	4172	4172	0	0
GntImpliesReady_A	1515211272	409731911	0	0
GntImpliesValid_A	1515211272	409731911	0	0
GrantKnown_A	1515211272	1511820768	0	0
IdxKnown_A	1515211272	1511820768	0	0
IndexIsCorrect_A	1515211272	409731911	0	0
NoReadyValidNoGrant_A	1515211272	177585470	0	0
Priority_A	1515211272	433376555	0	0
ReadyAndValidImplyGrant_A	1515211272	409731911	0	0
ReqAndReadyImplyGrant_A	1515211272	409731911	0	0
ReqImpliesValid_A	1515211272	433376555	0	0
ValidKnown_A	1515211272	1511820768	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	1511820768	0	0
T1	530176	529928	0	0
T2	15184	14804	0	0
T3	609708	508172	0	0
T7	525564	525200	0	0
T11	2756	2456	0	0
T12	14708	11856	0	0
T15	15088	12444	0	0
T16	5488	5228	0	0
T17	4152	3356	0	0
T18	4400	4112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4172	4172	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T7	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	409731911	0	0
T1	265088	2128	0	0
T2	15184	2436	0	0
T3	609708	0	0	0
T4	0	265408	0	0
T5	0	16666	0	0
T6	0	42322	0	0
T7	525564	56270	0	0
T11	2756	90	0	0
T12	14708	352	0	0
T15	15088	282	0	0
T16	5488	64	0	0
T17	4152	132	0	0
T18	4400	84	0	0
T22	0	6	0	0
T24	0	3226	0	0
T25	0	28918	0	0
T37	0	28	0	0
T38	414888	88906	0	0
T52	0	205320	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	409731911	0	0
T1	265088	2128	0	0
T2	15184	2436	0	0
T3	609708	0	0	0
T4	0	265408	0	0
T5	0	16666	0	0
T6	0	42322	0	0
T7	525564	56270	0	0
T11	2756	90	0	0
T12	14708	352	0	0
T15	15088	282	0	0
T16	5488	64	0	0
T17	4152	132	0	0
T18	4400	84	0	0
T22	0	6	0	0
T24	0	3226	0	0
T25	0	28918	0	0
T37	0	28	0	0
T38	414888	88906	0	0
T52	0	205320	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	1511820768	0	0
T1	530176	529928	0	0
T2	15184	14804	0	0
T3	609708	508172	0	0
T7	525564	525200	0	0
T11	2756	2456	0	0
T12	14708	11856	0	0
T15	15088	12444	0	0
T16	5488	5228	0	0
T17	4152	3356	0	0
T18	4400	4112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	1511820768	0	0
T1	530176	529928	0	0
T2	15184	14804	0	0
T3	609708	508172	0	0
T7	525564	525200	0	0
T11	2756	2456	0	0
T12	14708	11856	0	0
T15	15088	12444	0	0
T16	5488	5228	0	0
T17	4152	3356	0	0
T18	4400	4112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	409731911	0	0
T1	265088	2128	0	0
T2	15184	2436	0	0
T3	609708	0	0	0
T4	0	265408	0	0
T5	0	16666	0	0
T6	0	42322	0	0
T7	525564	56270	0	0
T11	2756	90	0	0
T12	14708	352	0	0
T15	15088	282	0	0
T16	5488	64	0	0
T17	4152	132	0	0
T18	4400	84	0	0
T22	0	6	0	0
T24	0	3226	0	0
T25	0	28918	0	0
T37	0	28	0	0
T38	414888	88906	0	0
T52	0	205320	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	177585470	0	0
T1	265088	2688	0	0
T2	15184	286	0	0
T3	609708	0	0	0
T4	0	516	0	0
T5	0	20720	0	0
T6	0	64722	0	0
T7	525564	256	0	0
T11	2756	324	0	0
T12	14708	1408	0	0
T15	15088	1116	0	0
T16	5488	256	0	0
T17	4152	528	0	0
T18	4400	286	0	0
T20	0	864	0	0
T22	0	24	0	0
T24	0	190	0	0
T25	0	931778	0	0
T37	0	44	0	0
T38	414888	7324	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	433376555	0	0
T1	265088	2128	0	0
T2	15184	2436	0	0
T3	609708	0	0	0
T4	0	265440	0	0
T5	0	21440	0	0
T6	0	52568	0	0
T7	525564	56270	0	0
T11	2756	90	0	0
T12	14708	352	0	0
T15	15088	282	0	0
T16	5488	64	0	0
T17	4152	132	0	0
T18	4400	84	0	0
T22	0	6	0	0
T24	0	3226	0	0
T25	0	282464	0	0
T37	0	28	0	0
T38	414888	88906	0	0
T52	0	205320	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	409731911	0	0
T1	265088	2128	0	0
T2	15184	2436	0	0
T3	609708	0	0	0
T4	0	265408	0	0
T5	0	16666	0	0
T6	0	42322	0	0
T7	525564	56270	0	0
T11	2756	90	0	0
T12	14708	352	0	0
T15	15088	282	0	0
T16	5488	64	0	0
T17	4152	132	0	0
T18	4400	84	0	0
T22	0	6	0	0
T24	0	3226	0	0
T25	0	28918	0	0
T37	0	28	0	0
T38	414888	88906	0	0
T52	0	205320	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	409731911	0	0
T1	265088	2128	0	0
T2	15184	2436	0	0
T3	609708	0	0	0
T4	0	265408	0	0
T5	0	16666	0	0
T6	0	42322	0	0
T7	525564	56270	0	0
T11	2756	90	0	0
T12	14708	352	0	0
T15	15088	282	0	0
T16	5488	64	0	0
T17	4152	132	0	0
T18	4400	84	0	0
T22	0	6	0	0
T24	0	3226	0	0
T25	0	28918	0	0
T37	0	28	0	0
T38	414888	88906	0	0
T52	0	205320	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	433376555	0	0
T1	265088	2128	0	0
T2	15184	2436	0	0
T3	609708	0	0	0
T4	0	265440	0	0
T5	0	21440	0	0
T6	0	52568	0	0
T7	525564	56270	0	0
T11	2756	90	0	0
T12	14708	352	0	0
T15	15088	282	0	0
T16	5488	64	0	0
T17	4152	132	0	0
T18	4400	84	0	0
T22	0	6	0	0
T24	0	3226	0	0
T25	0	282464	0	0
T37	0	28	0	0
T38	414888	88906	0	0
T52	0	205320	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1515211272	1511820768	0	0
T1	530176	529928	0	0
T2	15184	14804	0	0
T3	609708	508172	0	0
T7	525564	525200	0	0
T11	2756	2456	0	0
T12	14708	11856	0	0
T15	15088	12444	0	0
T16	5488	5228	0	0
T17	4152	3356	0	0
T18	4400	4112	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T15
1	0	Covered	T18,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T18,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T18,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T15
1	1	Covered	T18,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T4,T5
1	1	Covered	T1,T2,T15

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T18,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T18,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378802818	377955192	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	378802818	98342238	0	0
GntImpliesValid_A	378802818	98342238	0	0
GrantKnown_A	378802818	377955192	0	0
IdxKnown_A	378802818	377955192	0	0
IndexIsCorrect_A	378802818	98342238	0	0
NoReadyValidNoGrant_A	378802818	44883575	0	0
Priority_A	378802818	104337610	0	0
ReadyAndValidImplyGrant_A	378802818	98342238	0	0
ReqAndReadyImplyGrant_A	378802818	98342238	0	0
ReqImpliesValid_A	378802818	104337610	0	0
ValidKnown_A	378802818	377955192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	98342238	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	98342238	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	98342238	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	44883575	0	0
T1	132544	1344	0	0
T2	3796	128	0	0
T3	152427	0	0	0
T7	131391	128	0	0
T11	689	162	0	0
T12	3677	704	0	0
T15	3772	558	0	0
T16	1372	128	0	0
T17	1038	264	0	0
T18	1100	143	0	0
T38	0	1886	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	104337610	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	98342238	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	98342238	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	104337610	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T15
1	0	Covered	T18,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T18,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T18,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T15
1	1	Covered	T18,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T4,T5
1	1	Covered	T1,T2,T15

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T18,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T18,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378802818	377955192	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	378802818	98342229	0	0
GntImpliesValid_A	378802818	98342229	0	0
GrantKnown_A	378802818	377955192	0	0
IdxKnown_A	378802818	377955192	0	0
IndexIsCorrect_A	378802818	98342229	0	0
NoReadyValidNoGrant_A	378802818	44883501	0	0
Priority_A	378802818	104337675	0	0
ReadyAndValidImplyGrant_A	378802818	98342229	0	0
ReqAndReadyImplyGrant_A	378802818	98342229	0	0
ReqImpliesValid_A	378802818	104337675	0	0
ValidKnown_A	378802818	377955192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	98342229	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	98342229	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	98342229	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	44883501	0	0
T1	132544	1344	0	0
T2	3796	128	0	0
T3	152427	0	0	0
T7	131391	128	0	0
T11	689	162	0	0
T12	3677	704	0	0
T15	3772	558	0	0
T16	1372	128	0	0
T17	1038	264	0	0
T18	1100	143	0	0
T38	0	1886	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	104337675	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	98342229	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	98342229	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	104337675	0	0
T1	132544	1064	0	0
T2	3796	690	0	0
T3	152427	0	0	0
T7	131391	28135	0	0
T11	689	45	0	0
T12	3677	176	0	0
T15	3772	141	0	0
T16	1372	32	0	0
T17	1038	66	0	0
T18	1100	42	0	0
T38	0	22299	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T38,T4
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T38,T4
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T38,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T38,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378802818	377955192	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	378802818	106523684	0	0
GntImpliesValid_A	378802818	106523684	0	0
GrantKnown_A	378802818	377955192	0	0
IdxKnown_A	378802818	377955192	0	0
IndexIsCorrect_A	378802818	106523684	0	0
NoReadyValidNoGrant_A	378802818	43909200	0	0
Priority_A	378802818	112350594	0	0
ReadyAndValidImplyGrant_A	378802818	106523684	0	0
ReqAndReadyImplyGrant_A	378802818	106523684	0	0
ReqImpliesValid_A	378802818	112350594	0	0
ValidKnown_A	378802818	377955192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	106523684	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132704	0	0
T5	0	8333	0	0
T6	0	21161	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	14459	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	106523684	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132704	0	0
T5	0	8333	0	0
T6	0	21161	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	14459	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	106523684	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132704	0	0
T5	0	8333	0	0
T6	0	21161	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	14459	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	43909200	0	0
T2	3796	15	0	0
T3	152427	0	0	0
T4	0	258	0	0
T5	0	10360	0	0
T6	0	32361	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T20	0	432	0	0
T22	0	12	0	0
T24	0	95	0	0
T25	0	465889	0	0
T37	0	22	0	0
T38	207444	1776	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	112350594	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132720	0	0
T5	0	10720	0	0
T6	0	26284	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	141232	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	106523684	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132704	0	0
T5	0	8333	0	0
T6	0	21161	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	14459	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	106523684	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132704	0	0
T5	0	8333	0	0
T6	0	21161	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	14459	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	112350594	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132720	0	0
T5	0	10720	0	0
T6	0	26284	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	141232	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T38,T4
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T38,T4
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T38,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T38,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	378802818	377955192	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	378802818	106523760	0	0
GntImpliesValid_A	378802818	106523760	0	0
GrantKnown_A	378802818	377955192	0	0
IdxKnown_A	378802818	377955192	0	0
IndexIsCorrect_A	378802818	106523760	0	0
NoReadyValidNoGrant_A	378802818	43909194	0	0
Priority_A	378802818	112350676	0	0
ReadyAndValidImplyGrant_A	378802818	106523760	0	0
ReqAndReadyImplyGrant_A	378802818	106523760	0	0
ReqImpliesValid_A	378802818	112350676	0	0
ValidKnown_A	378802818	377955192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	106523760	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132704	0	0
T5	0	8333	0	0
T6	0	21161	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	14459	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	106523760	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132704	0	0
T5	0	8333	0	0
T6	0	21161	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	14459	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	106523760	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132704	0	0
T5	0	8333	0	0
T6	0	21161	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	14459	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	43909194	0	0
T2	3796	15	0	0
T3	152427	0	0	0
T4	0	258	0	0
T5	0	10360	0	0
T6	0	32361	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T20	0	432	0	0
T22	0	12	0	0
T24	0	95	0	0
T25	0	465889	0	0
T37	0	22	0	0
T38	207444	1776	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	112350676	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132720	0	0
T5	0	10720	0	0
T6	0	26284	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	141232	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	106523760	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132704	0	0
T5	0	8333	0	0
T6	0	21161	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	14459	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	106523760	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132704	0	0
T5	0	8333	0	0
T6	0	21161	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	14459	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	112350676	0	0
T2	3796	528	0	0
T3	152427	0	0	0
T4	0	132720	0	0
T5	0	10720	0	0
T6	0	26284	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T22	0	3	0	0
T24	0	1613	0	0
T25	0	141232	0	0
T37	0	14	0	0
T38	207444	22154	0	0
T52	0	102660	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	377955192	0	0
T1	132544	132482	0	0
T2	3796	3701	0	0
T3	152427	127043	0	0
T7	131391	131300	0	0
T11	689	614	0	0
T12	3677	2964	0	0
T15	3772	3111	0	0
T16	1372	1307	0	0
T17	1038	839	0	0
T18	1100	1028	0	0