Unified Coverage Report :: Module :: flash_phy_rd_buffers

Module : flash_phy_rd_buffers

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf	94.64	100.00	78.57			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.65	100.00	90.59			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.65	100.00	90.59			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.65	100.00	90.59			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.65	100.00	90.59			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.70	100.00	90.81			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.70	100.00	90.81			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.70	100.00	90.81			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.70	100.00	90.81			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Module : flash_phy_rd_buffers

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T60,T67

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T11

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T38,T4,T24

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T1,T2,T11

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T1,T2,T11

---

Branch Coverage for Module : flash_phy_rd_buffers

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T60,T67
0	0	1	-	-	Covered	T38,T4,T24
0	0	0	1	-	Covered	T1,T2,T11
0	0	0	0	1	Covered	T1,T2,T11
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buffers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	2147483647	5147868	0	0
UpdateCheck_A	2147483647	5147858	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5147868	0	0
T1	530176	256	0	0
T2	30368	5	0	0
T3	1219416	0	0	0
T4	0	110	0	0
T5	0	21053	0	0
T6	0	17669	0	0
T7	1051128	0	0	0
T11	5512	7	0	0
T12	29416	0	0	0
T15	30176	0	0	0
T16	10976	0	0	0
T17	8304	0	0	0
T18	8800	5	0	0
T20	0	95	0	0
T22	0	3	0	0
T24	0	117	0	0
T25	0	23553	0	0
T30	0	256	0	0
T34	0	130	0	0
T37	0	8	0	0
T38	829776	1178	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5147858	0	0
T1	530176	256	0	0
T2	30368	5	0	0
T3	1219416	0	0	0
T4	0	110	0	0
T5	0	21053	0	0
T6	0	17669	0	0
T7	1051128	0	0	0
T11	5512	7	0	0
T12	29416	0	0	0
T15	30176	0	0	0
T16	10976	0	0	0
T17	8304	0	0	0
T18	8800	5	0	0
T20	0	95	0	0
T22	0	3	0	0
T24	0	117	0	0
T25	0	23553	0	0
T30	0	256	0	0
T34	0	130	0	0
T37	0	8	0	0
T38	829776	1178	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T60,T67

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T18

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T38,T24,T30

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T1,T11,T18

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T1,T11,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T60,T67
0	0	1	-	-	Covered	T38,T24,T30
0	0	0	1	-	Covered	T1,T11,T18
0	0	0	0	1	Covered	T1,T11,T18
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	378802818	586629	0	0
UpdateCheck_A	378802818	586629	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	586629	0	0
T1	132544	64	0	0
T2	3796	0	0	0
T3	152427	0	0	0
T4	0	15	0	0
T5	0	3173	0	0
T6	0	2201	0	0
T7	131391	0	0	0
T11	689	2	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	2	0	0
T24	0	22	0	0
T25	0	2977	0	0
T30	0	64	0	0
T38	0	149	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	586629	0	0
T1	132544	64	0	0
T2	3796	0	0	0
T3	152427	0	0	0
T4	0	15	0	0
T5	0	3173	0	0
T6	0	2201	0	0
T7	131391	0	0	0
T11	689	2	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	2	0	0
T24	0	22	0	0
T25	0	2977	0	0
T30	0	64	0	0
T38	0	149	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T60,T67

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T18

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T38,T24,T30

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T1,T11,T18

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T1,T11,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T60,T67
0	0	1	-	-	Covered	T38,T24,T30
0	0	0	1	-	Covered	T1,T11,T18
0	0	0	0	1	Covered	T1,T11,T18
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	378802818	586594	0	0
UpdateCheck_A	378802818	586593	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	586594	0	0
T1	132544	64	0	0
T2	3796	0	0	0
T3	152427	0	0	0
T4	0	13	0	0
T5	0	3186	0	0
T6	0	2207	0	0
T7	131391	0	0	0
T11	689	2	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	1	0	0
T24	0	22	0	0
T25	0	2966	0	0
T30	0	64	0	0
T38	0	149	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	586593	0	0
T1	132544	64	0	0
T2	3796	0	0	0
T3	152427	0	0	0
T4	0	13	0	0
T5	0	3186	0	0
T6	0	2207	0	0
T7	131391	0	0	0
T11	689	2	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	1	0	0
T24	0	22	0	0
T25	0	2966	0	0
T30	0	64	0	0
T38	0	149	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T60,T68

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T18

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T38,T30,T69

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T1,T11,T18

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T1,T11,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T60,T9
0	0	1	-	-	Covered	T38,T30,T69
0	0	0	1	-	Covered	T1,T11,T18
0	0	0	0	1	Covered	T1,T11,T18
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	378802818	586417	0	0
UpdateCheck_A	378802818	586416	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	586417	0	0
T1	132544	64	0	0
T2	3796	0	0	0
T3	152427	0	0	0
T4	0	14	0	0
T5	0	3185	0	0
T6	0	2204	0	0
T7	131391	0	0	0
T11	689	2	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	1	0	0
T24	0	21	0	0
T25	0	2988	0	0
T30	0	64	0	0
T38	0	149	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	586416	0	0
T1	132544	64	0	0
T2	3796	0	0	0
T3	152427	0	0	0
T4	0	14	0	0
T5	0	3185	0	0
T6	0	2204	0	0
T7	131391	0	0	0
T11	689	2	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	1	0	0
T24	0	21	0	0
T25	0	2988	0	0
T30	0	64	0	0
T38	0	149	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T11,T60,T68

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T11,T18

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T38,T24,T30

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T1,T11,T18

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T1,T11,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T11,T60,T9
0	0	1	-	-	Covered	T38,T24,T30
0	0	0	1	-	Covered	T1,T11,T18
0	0	0	0	1	Covered	T1,T11,T18
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	378802818	586129	0	0
UpdateCheck_A	378802818	586126	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	586129	0	0
T1	132544	64	0	0
T2	3796	0	0	0
T3	152427	0	0	0
T4	0	14	0	0
T5	0	3181	0	0
T6	0	2205	0	0
T7	131391	0	0	0
T11	689	1	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	1	0	0
T24	0	22	0	0
T25	0	2983	0	0
T30	0	64	0	0
T38	0	139	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	586126	0	0
T1	132544	64	0	0
T2	3796	0	0	0
T3	152427	0	0	0
T4	0	14	0	0
T5	0	3181	0	0
T6	0	2205	0	0
T7	131391	0	0	0
T11	689	1	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	1	0	0
T24	0	22	0	0
T25	0	2983	0	0
T30	0	64	0	0
T38	0	139	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T38,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T70,T68,T71

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T38,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T38,T4,T49

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T2,T38,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T2,T38,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T70,T9,T68
0	0	1	-	-	Covered	T38,T4,T49
0	0	0	1	-	Covered	T2,T38,T4
0	0	0	0	1	Covered	T2,T38,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	378802818	700687	0	0
UpdateCheck_A	378802818	700684	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	700687	0	0
T2	3796	2	0	0
T3	152427	0	0	0
T4	0	14	0	0
T5	0	2082	0	0
T6	0	2215	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T20	0	25	0	0
T22	0	1	0	0
T24	0	7	0	0
T25	0	2915	0	0
T37	0	2	0	0
T38	207444	151	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	700684	0	0
T2	3796	2	0	0
T3	152427	0	0	0
T4	0	14	0	0
T5	0	2082	0	0
T6	0	2215	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T20	0	25	0	0
T22	0	1	0	0
T24	0	7	0	0
T25	0	2915	0	0
T37	0	2	0	0
T38	207444	151	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T38,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T70,T68,T71

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T38,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T38,T4,T24

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T2,T38,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T2,T38,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T70,T9,T68
0	0	1	-	-	Covered	T38,T4,T24
0	0	0	1	-	Covered	T2,T38,T4
0	0	0	0	1	Covered	T2,T38,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	378802818	700685	0	0
UpdateCheck_A	378802818	700685	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	700685	0	0
T2	3796	1	0	0
T3	152427	0	0	0
T4	0	14	0	0
T5	0	2082	0	0
T6	0	2211	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T20	0	24	0	0
T22	0	1	0	0
T24	0	8	0	0
T25	0	2903	0	0
T37	0	2	0	0
T38	207444	151	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	700685	0	0
T2	3796	1	0	0
T3	152427	0	0	0
T4	0	14	0	0
T5	0	2082	0	0
T6	0	2211	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T20	0	24	0	0
T22	0	1	0	0
T24	0	8	0	0
T25	0	2903	0	0
T37	0	2	0	0
T38	207444	151	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T38,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T70,T68,T71

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T38,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T38,T4,T49

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T2,T38,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T2,T38,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T70,T9,T68
0	0	1	-	-	Covered	T38,T4,T49
0	0	0	1	-	Covered	T2,T38,T4
0	0	0	0	1	Covered	T2,T38,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	378802818	700493	0	0
UpdateCheck_A	378802818	700492	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	700493	0	0
T2	3796	1	0	0
T3	152427	0	0	0
T4	0	13	0	0
T5	0	2082	0	0
T6	0	2215	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T20	0	24	0	0
T22	0	1	0	0
T24	0	7	0	0
T25	0	2912	0	0
T37	0	2	0	0
T38	207444	150	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	700492	0	0
T2	3796	1	0	0
T3	152427	0	0	0
T4	0	13	0	0
T5	0	2082	0	0
T6	0	2215	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T20	0	24	0	0
T22	0	1	0	0
T24	0	7	0	0
T25	0	2912	0	0
T37	0	2	0	0
T38	207444	150	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	38	23	23	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T38,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T70,T68,T71

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T38,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T38,T4,T24

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T2,T38,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Not Covered
1	1	Covered	T2,T38,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	38	6	6	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	38	if ((!rst_ni))
-2-:	45	if (((!en_i) && (out_o.attr != Invalid)))
-3-:	48	if ((wipe_i && en_i))
-4-:	51	if ((alloc_i && en_i))
-5-:	57	if ((update_i && en_i))

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T70,T9,T68
0	0	1	-	-	Covered	T38,T4,T24
0	0	0	1	-	Covered	T2,T38,T4
0	0	0	0	1	Covered	T2,T38,T4
0	0	0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllocCheck_A	378802818	700234	0	0
UpdateCheck_A	378802818	700233	0	0

AllocCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	700234	0	0
T2	3796	1	0	0
T3	152427	0	0	0
T4	0	13	0	0
T5	0	2082	0	0
T6	0	2211	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T20	0	22	0	0
T24	0	8	0	0
T25	0	2909	0	0
T34	0	130	0	0
T37	0	2	0	0
T38	207444	140	0	0

UpdateCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378802818	700233	0	0
T2	3796	1	0	0
T3	152427	0	0	0
T4	0	13	0	0
T5	0	2082	0	0
T6	0	2211	0	0
T7	131391	0	0	0
T11	689	0	0	0
T12	3677	0	0	0
T15	3772	0	0	0
T16	1372	0	0	0
T17	1038	0	0	0
T18	1100	0	0	0
T20	0	22	0	0
T24	0	8	0	0
T25	0	2909	0	0
T34	0	130	0	0
T37	0	2	0	0
T38	207444	140	0	0