Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	280366	1		T2	1		T3	2		T21	1
all_values[1]	280366	1		T2	1		T3	2		T21	1
all_values[2]	280366	1		T2	1		T3	2		T21	1
all_values[3]	280366	1		T2	1		T3	2		T21	1
all_values[4]	280366	1		T2	1		T3	2		T21	1
all_values[5]	280366	1		T2	1		T3	2		T21	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	567033	1		T2	6		T3	12		T21	6
auto[1]	1115163	1		T6	25204		T41	6832		T32	6592

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	824460	1		T2	4		T3	7		T21	4
auto[1]	857736	1		T2	2		T3	5		T21	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	280206	1		T2	1		T3	2		T21	1
all_values[0]	auto[1]	auto[1]	160	1		T264	1		T265	2		T319	2
all_values[1]	auto[0]	auto[1]	280226	1		T2	1		T3	2		T21	1
all_values[1]	auto[1]	auto[1]	140	1		T264	1		T265	4		T320	1
all_values[2]	auto[0]	auto[0]	1602	1		T2	1		T3	2		T21	1
all_values[2]	auto[0]	auto[1]	53	1		T265	2		T319	1		T320	1
all_values[2]	auto[1]	auto[0]	278655	1		T6	6301		T41	1708		T32	1648
all_values[2]	auto[1]	auto[1]	56	1		T264	1		T320	1		T322	1
all_values[3]	auto[0]	auto[0]	1598	1		T2	1		T3	2		T21	1
all_values[3]	auto[0]	auto[1]	54	1		T264	1		T265	1		T323	1
all_values[3]	auto[1]	auto[0]	91118	1		T6	59		T41	854		T32	1648
all_values[3]	auto[1]	auto[1]	187596	1		T6	6242		T41	854		T38	1715
all_values[4]	auto[0]	auto[0]	1115	1		T2	1		T3	1		T21	1
all_values[4]	auto[0]	auto[1]	521	1		T3	1		T23	1		T13	1
all_values[4]	auto[1]	auto[0]	170237	1		T6	4740		T41	854		T32	1
all_values[4]	auto[1]	auto[1]	108493	1		T6	1561		T41	854		T32	1647
all_values[5]	auto[0]	auto[0]	1500	1		T2	1		T3	2		T21	1
all_values[5]	auto[0]	auto[1]	158	1		T42	1		T44	1		T45	1
all_values[5]	auto[1]	auto[0]	278635	1		T6	6301		T41	1708		T32	1648
all_values[5]	auto[1]	auto[1]	73	1		T264	1		T265	1		T323	2