Unified Coverage Report

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A	0	0	412840103	0	0	0
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A	0	0	412840103	0	0	0
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A	0	0	412840103	0	0	0
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A	0	0	412840103	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A	0	0	412840103	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A	0	0	412840103	0	0	0
tb.dut.FpvSecCmRdReqFifoRptrCheck_A	0	0	412840103	0	0	0
tb.dut.FpvSecCmRdReqFifoWptrCheck_A	0	0	412840103	0	0	0
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A	0	0	412840103	0	0	0
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A	0	0	412840103	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	412840103	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	412840103	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	412840103	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	412840103	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	412840103	0	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	412840103	0	0	1033
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	412840103	0	0	1033
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	412840103	0	0	1033
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	412840103	0	0	1033
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	412840103	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	412840103	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	412840103	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	412840103	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	412840103	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	412840103	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	412840103	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	412840103	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1040	1040	0	0
tb.dut.FlashAddrKnown_A	0	0	412840103	277735826	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	412840103	412021190	0	0
tb.dut.FlashKnownO_A	0	0	412840103	412021190	0	0
tb.dut.FlashProgKnown_A	0	0	412840103	160384646	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	412840103	412021190	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmRdRspFifoRptrCheck_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmRdRspFifoWptrCheck_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	412840103	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	412840103	50	0	0
tb.dut.IntrErrO_A	0	0	412840103	412021190	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	412840103	412021190	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	412840103	412021190	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	412840103	412021190	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	412840103	412021190	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	412840103	412021190	0	0
tb.dut.MemRspPayLoad_A	0	0	412840103	5653706	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	412840103	412021190	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	412840103	412021190	0	0
tb.dut.MemTlDValidKnownO_A	0	0	412840103	412021190	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	412840103	412021190	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	412840103	412021190	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	412840103	412021190	0	0
tb.dut.RspPayLoad_A	0	0	412519555	46252638	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	412840103	412021190	0	0
tb.dut.TdoEnIsOne_A	0	0	412840103	412021190	0	0
tb.dut.TdoKnown_A	0	0	412840103	412021190	0	0
tb.dut.TlAReadyKnownO_A	0	0	412840103	412021190	0	0
tb.dut.TlDValidKnownO_A	0	0	412840103	412021190	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	415198468	3915	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	415198468	1045	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	415198468	1810	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	415198468	1656	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	415198468	1526	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	415198468	1523	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	415198468	1679	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	415198468	1637	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	415198468	1500	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	415198468	1573	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	415198468	1470	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	415198468	1871	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	415198468	934	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	415198468	913	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	415198468	955	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	415198468	865	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	415198468	917	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	415198468	1060	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	415198468	861	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	415198468	926	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	415198468	919	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	415198468	971	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	415198468	1523	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	415198468	969	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	415198468	1723	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	415198468	1751	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	415198468	890	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	415198468	946	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	415198468	1549	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	415198468	1523	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	415198468	1651	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	415198468	1706	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	415198468	1473	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	415198468	1581	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	415198468	1559	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	415198468	1648	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	415198468	1470	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	415198468	1543	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	415198468	954	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	415198468	952	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	415198468	850	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	415198468	899	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	415198468	935	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	415198468	896	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	415198468	902	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	415198468	916	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	415198468	851	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	415198468	975	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	415198468	1436	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	415198468	953	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	415198468	1664	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	415198468	1674	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	415198468	812	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	415198468	1054	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	415198468	878	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	415198468	1453	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	415198468	885	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	415198468	1000	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	415198468	800	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	415198468	1033	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	415198468	1479	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	415198468	923	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	415198468	1137	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	415198468	998	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	415198468	954	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	415198468	994	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	415198468	968	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	415198468	886	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	415198468	1020	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	415198468	1647	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	415198468	1493	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	415198468	1710	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	415198468	1675	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	415198468	1391	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	415198468	1663	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	415198468	1659	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	415198468	1619	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	415198468	199	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	415198468	836	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	415198468	884	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	415198468	959	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	415198468	845	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	415198468	940	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	415198468	924	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	415198468	803	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	415198468	882	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	415198468	744	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	412840103	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	412840103	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	412840103	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	412840103	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	412840103	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	412840103	20	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	415198431	36018217	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	415198431	414294582	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	415198431	414294582	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	415198431	46959125	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	415198431	414294582	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	415198431	414294582	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
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tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	1250	1250	0	0

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	NUMBER	PERCENT
Total Number	1020	100.00
Uncovered	27	2.65
Success	993	97.35
Failure	0	0.00
Incomplete	15	1.47
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	3	30.00
All Matches	7	70.00
First Matches	7	70.00

	ASSERT	PROPERTIES	SEQUENCES
Total	1020	0	10
Category 0	1020	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	1020	0	10
Severity 0	1020	0	10