Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	238934	1		T2	118		T3	36		T4	32
auto[FlashEraseBank]	269121	1		T2	118		T3	9		T4	16

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	258868	1		T3	45		T4	33		T5	14
auto[FlashOpProgram]	230059	1		T2	236		T5	2		T23	3
auto[FlashOpErase]	15128	1		T4	15		T23	1		T30	19
auto[FlashOpInvalid]	4000	1		T134	200		T272	200		T288	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	258868	1		T3	45		T4	33		T5	14
op[FlashOpProgram]	230059	1		T2	236		T5	2		T23	3
op[FlashOpErase]	15128	1		T4	15		T23	1		T30	19
read_erase_read	521	1		T4	10		T30	16		T64	2
read_prog_read	845	1		T5	2		T64	4		T29	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	371337	1		T2	236		T3	45		T4	22
auto[FlashPartInfo]	133211	1		T4	22		T5	7		T30	33
auto[FlashPartInfo1]	882	1		T7	2		T49	2		T41	9
auto[FlashPartInfo2]	2625	1		T4	4		T5	4		T36	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	188861	1		T3	45		T4	14		T5	4
auto[FlashPartData]	auto[FlashOpProgram]	174929	1		T2	236		T5	1		T23	3
auto[FlashPartData]	auto[FlashOpErase]	3627	1		T4	8		T23	1		T30	8
auto[FlashPartData]	auto[FlashOpInvalid]	3920	1		T134	194		T272	196		T288	196
auto[FlashPartInfo]	auto[FlashOpRead]	67597	1		T4	16		T5	7		T30	22
auto[FlashPartInfo]	auto[FlashOpProgram]	54073	1		T13	2		T64	673		T29	1
auto[FlashPartInfo]	auto[FlashOpErase]	11469	1		T4	6		T30	11		T13	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	72	1		T134	4		T272	4		T288	4
auto[FlashPartInfo1]	auto[FlashOpRead]	711	1		T7	2		T49	2		T41	9
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T138	32		T140	32		T392	1
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T141	1		T393	1		T394	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T141	2		T394	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1699	1		T4	3		T5	3		T31	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	893	1		T5	1		T49	9		T126	1
auto[FlashPartInfo2]	auto[FlashOpErase]	29	1		T4	1		T36	1		T134	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T134	2		T394	2		-	-