Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29925	1		T30	6		T64	16		T36	20
auto[1]	35	1		T4	2		T29	1		T63	1
auto[2]	53	1		T30	4		T126	2		T72	8
auto[3]	228	1		T4	9		T5	1		T30	8

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7567	1		T4	3		T5	1		T30	5
evic_idx[1]	7556	1		T4	2		T30	4		T64	4
evic_idx[2]	7552	1		T4	3		T30	5		T64	4
evic_idx[3]	7566	1		T4	3		T30	4		T64	4

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29194	1		T4	11		T30	18		T52	480
evic_op[2]	314	1		T5	1		T29	1		T36	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7243	1		T30	3		T52	120		T27	3
evic_idx[0]	evic_op[1]	auto[1]	4	1		T395	1		T396	2		T397	1
evic_idx[0]	evic_op[1]	auto[2]	8	1		T30	1		T395	2		T398	1
evic_idx[0]	evic_op[1]	auto[3]	46	1		T4	3		T30	1		T108	2
evic_idx[0]	evic_op[2]	auto[0]	63	1		T36	1		T37	1		T27	4
evic_idx[0]	evic_op[2]	auto[1]	5	1		T29	1		T399	1		T400	1
evic_idx[0]	evic_op[2]	auto[2]	4	1		T126	1		T401	1		T402	1
evic_idx[0]	evic_op[2]	auto[3]	10	1		T5	1		T126	1		T195	1
evic_idx[1]	evic_op[1]	auto[0]	7241	1		T30	1		T52	120		T27	3
evic_idx[1]	evic_op[1]	auto[1]	3	1		T396	3		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	6	1		T30	1		T403	1		T395	2
evic_idx[1]	evic_op[1]	auto[3]	50	1		T4	2		T30	2		T108	4
evic_idx[1]	evic_op[2]	auto[0]	62	1		T36	1		T37	1		T27	4
evic_idx[1]	evic_op[2]	auto[1]	4	1		T63	1		T404	1		T405	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T126	1		T406	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	5	1		T31	1		T185	1		T196	1
evic_idx[2]	evic_op[1]	auto[0]	7241	1		T30	1		T52	120		T27	3
evic_idx[2]	evic_op[1]	auto[1]	4	1		T4	1		T396	3		-	-
evic_idx[2]	evic_op[1]	auto[2]	2	1		T30	1		T403	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	48	1		T4	2		T30	3		T108	4
evic_idx[2]	evic_op[2]	auto[0]	60	1		T36	1		T37	1		T27	4
evic_idx[2]	evic_op[2]	auto[1]	7	1		T407	1		T405	1		T408	1
evic_idx[2]	evic_op[2]	auto[2]	1	1		T409	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	6	1		T61	1		T257	1		T197	1
evic_idx[3]	evic_op[1]	auto[0]	7244	1		T30	1		T52	120		T27	3
evic_idx[3]	evic_op[1]	auto[1]	4	1		T4	1		T396	2		T410	1
evic_idx[3]	evic_op[1]	auto[2]	4	1		T30	1		T395	1		T398	2
evic_idx[3]	evic_op[1]	auto[3]	46	1		T4	2		T30	2		T108	1
evic_idx[3]	evic_op[2]	auto[0]	62	1		T36	1		T37	1		T27	4
evic_idx[3]	evic_op[2]	auto[1]	4	1		T411	1		T412	1		T413	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T187	1		T402	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	17	1		T187	1		T46	1		T414	1