Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	7526	1		T54	2727		T327	1961		T328	1265
rd_lvl[2]	27466	1		T54	2404		T329	10620		T327	793
rd_lvl[3]	16003	1		T54	1365		T329	370		T330	910
rd_lvl[4]	30480	1		T6	2749		T54	1626		T331	1525
rd_lvl[5]	8496	1		T6	1419		T54	1485		T277	893
rd_lvl[6]	14474	1		T6	701		T54	24		T277	245
rd_lvl[7]	12770	1		T6	303		T54	1419		T331	56
rd_lvl[8]	14062	1		T6	999		T54	1417		T332	1140
rd_lvl[9]	8621	1		T41	330		T54	1977		T215	542
rd_lvl[10]	11847	1		T41	524		T54	854		T215	956
rd_lvl[11]	4650	1		T333	682		T277	99		T334	53
rd_lvl[12]	10666	1		T333	1017		T335	1724		T331	57
rd_lvl[13]	3563	1		T336	111		T337	216		T330	20
rd_lvl[14]	7493	1		T38	1376		T337	113		T274	1
rd_lvl[15]	2446	1		T38	338		T39	49		T336	91