Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	280366	1		T2	1		T3	2		T21	1
all_pins[1]	280366	1		T2	1		T3	2		T21	1
all_pins[2]	280366	1		T2	1		T3	2		T21	1
all_pins[3]	280366	1		T2	1		T3	2		T21	1
all_pins[4]	280366	1		T2	1		T3	2		T21	1
all_pins[5]	280366	1		T2	1		T3	2		T21	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1383858	1		T2	6		T3	12		T21	6
values[0x1]	298338	1		T6	8744		T41	1708		T32	1647
transitions[0x0=>0x1]	273408	1		T6	6230		T41	1708		T32	1647
transitions[0x1=>0x0]	273396	1		T6	6230		T41	1708		T32	1647

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280206	1		T2	1		T3	2		T21	1
all_pins[0]	values[0x1]	160	1		T264	1		T265	2		T319	2
all_pins[0]	transitions[0x0=>0x1]	87	1		T265	1		T319	2		T322	2
all_pins[0]	transitions[0x1=>0x0]	67	1		T265	3		T322	2		T323	1
all_pins[1]	values[0x0]	280226	1		T2	1		T3	2		T21	1
all_pins[1]	values[0x1]	140	1		T264	1		T265	4		T320	1
all_pins[1]	transitions[0x0=>0x1]	115	1		T264	1		T265	4		T322	2
all_pins[1]	transitions[0x1=>0x0]	1427	1		T38	1		T39	20		T342	1084
all_pins[2]	values[0x0]	278914	1		T2	1		T3	2		T21	1
all_pins[2]	values[0x1]	1452	1		T38	1		T39	20		T342	1084
all_pins[2]	transitions[0x0=>0x1]	46	1		T264	1		T320	1		T323	1
all_pins[2]	transitions[0x1=>0x0]	180598	1		T6	6171		T41	854		T38	1714
all_pins[3]	values[0x0]	98362	1		T2	1		T3	2		T21	1
all_pins[3]	values[0x1]	182004	1		T6	6171		T41	854		T38	1715
all_pins[3]	transitions[0x0=>0x1]	158637	1		T6	3657		T41	854		T38	1714
all_pins[3]	transitions[0x1=>0x0]	91142	1		T6	59		T41	854		T32	1647
all_pins[4]	values[0x0]	165857	1		T2	1		T3	2		T21	1
all_pins[4]	values[0x1]	114509	1		T6	2573		T41	854		T32	1647
all_pins[4]	transitions[0x0=>0x1]	114493	1		T6	2573		T41	854		T32	1647
all_pins[4]	transitions[0x1=>0x0]	57	1		T323	2		T321	4		T325	3
all_pins[5]	values[0x0]	280293	1		T2	1		T3	2		T21	1
all_pins[5]	values[0x1]	73	1		T264	1		T265	1		T323	2
all_pins[5]	transitions[0x0=>0x1]	30	1		T323	1		T321	2		T343	1
all_pins[5]	transitions[0x1=>0x0]	105	1		T264	1		T265	2		T319	1