| T1078 |
/workspace/coverage/default/0.flash_ctrl_sec_info_access.2193506879 |
|
|
Jun 24 07:16:33 PM PDT 24 |
Jun 24 07:17:59 PM PDT 24 |
4889700000 ps |
| T1079 |
/workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.3596002708 |
|
|
Jun 24 07:22:44 PM PDT 24 |
Jun 24 07:23:15 PM PDT 24 |
85342200 ps |
| T1080 |
/workspace/coverage/default/10.flash_ctrl_mp_regions.2306257071 |
|
|
Jun 24 07:26:21 PM PDT 24 |
Jun 24 07:31:45 PM PDT 24 |
16361577200 ps |
| T1081 |
/workspace/coverage/default/6.flash_ctrl_smoke.1741487231 |
|
|
Jun 24 07:23:38 PM PDT 24 |
Jun 24 07:25:50 PM PDT 24 |
54442300 ps |
| T1082 |
/workspace/coverage/default/9.flash_ctrl_mp_regions.1730068972 |
|
|
Jun 24 07:25:46 PM PDT 24 |
Jun 24 07:34:58 PM PDT 24 |
13738367500 ps |
| T1083 |
/workspace/coverage/default/69.flash_ctrl_connect.1469671351 |
|
|
Jun 24 07:35:00 PM PDT 24 |
Jun 24 07:35:21 PM PDT 24 |
29215800 ps |
| T388 |
/workspace/coverage/default/29.flash_ctrl_sec_info_access.1411729029 |
|
|
Jun 24 07:32:36 PM PDT 24 |
Jun 24 07:34:02 PM PDT 24 |
4935140100 ps |
| T1084 |
/workspace/coverage/default/18.flash_ctrl_connect.761635121 |
|
|
Jun 24 07:30:54 PM PDT 24 |
Jun 24 07:31:12 PM PDT 24 |
22281800 ps |
| T1085 |
/workspace/coverage/default/48.flash_ctrl_otp_reset.2421172217 |
|
|
Jun 24 07:34:24 PM PDT 24 |
Jun 24 07:36:38 PM PDT 24 |
225807600 ps |
| T1086 |
/workspace/coverage/default/7.flash_ctrl_sec_info_access.131733722 |
|
|
Jun 24 07:25:15 PM PDT 24 |
Jun 24 07:26:34 PM PDT 24 |
3617159400 ps |
| T1087 |
/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3270527055 |
|
|
Jun 24 07:27:56 PM PDT 24 |
Jun 24 07:28:12 PM PDT 24 |
47240300 ps |
| T1088 |
/workspace/coverage/default/41.flash_ctrl_otp_reset.3351209672 |
|
|
Jun 24 07:33:48 PM PDT 24 |
Jun 24 07:36:02 PM PDT 24 |
131575400 ps |
| T1089 |
/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.467530614 |
|
|
Jun 24 07:30:21 PM PDT 24 |
Jun 24 07:32:36 PM PDT 24 |
1509896900 ps |
| T1090 |
/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.4007075670 |
|
|
Jun 24 07:25:44 PM PDT 24 |
Jun 24 07:28:26 PM PDT 24 |
6160306500 ps |
| T1091 |
/workspace/coverage/default/4.flash_ctrl_full_mem_access.1383544168 |
|
|
Jun 24 07:22:41 PM PDT 24 |
Jun 24 08:05:05 PM PDT 24 |
191216124000 ps |
| T1092 |
/workspace/coverage/default/16.flash_ctrl_smoke.2832727478 |
|
|
Jun 24 07:29:34 PM PDT 24 |
Jun 24 07:31:19 PM PDT 24 |
85823400 ps |
| T1093 |
/workspace/coverage/default/75.flash_ctrl_connect.3566948517 |
|
|
Jun 24 07:35:41 PM PDT 24 |
Jun 24 07:35:59 PM PDT 24 |
24229300 ps |
| T1094 |
/workspace/coverage/default/18.flash_ctrl_intr_rd.3723364454 |
|
|
Jun 24 07:30:50 PM PDT 24 |
Jun 24 07:33:05 PM PDT 24 |
1389827900 ps |
| T1095 |
/workspace/coverage/default/8.flash_ctrl_intr_wr.716008401 |
|
|
Jun 24 07:25:44 PM PDT 24 |
Jun 24 07:27:21 PM PDT 24 |
5870171100 ps |
| T1096 |
/workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2263091294 |
|
|
Jun 24 07:29:34 PM PDT 24 |
Jun 24 07:32:19 PM PDT 24 |
23209018500 ps |
| T1097 |
/workspace/coverage/default/39.flash_ctrl_intr_rd.2544890031 |
|
|
Jun 24 07:33:44 PM PDT 24 |
Jun 24 07:37:17 PM PDT 24 |
1561753100 ps |
| T1098 |
/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.2668063386 |
|
|
Jun 24 07:30:20 PM PDT 24 |
Jun 24 07:30:35 PM PDT 24 |
15498200 ps |
| T1099 |
/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4088027103 |
|
|
Jun 24 07:20:59 PM PDT 24 |
Jun 24 07:23:35 PM PDT 24 |
11800903400 ps |
| T162 |
/workspace/coverage/default/2.flash_ctrl_rma_err.503399074 |
|
|
Jun 24 07:20:41 PM PDT 24 |
Jun 24 07:35:52 PM PDT 24 |
41318939900 ps |
| T1100 |
/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.3964466978 |
|
|
Jun 24 07:17:48 PM PDT 24 |
Jun 24 07:31:55 PM PDT 24 |
50124442600 ps |
| T1101 |
/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.2601646106 |
|
|
Jun 24 07:30:20 PM PDT 24 |
Jun 24 07:30:35 PM PDT 24 |
46046800 ps |
| T1102 |
/workspace/coverage/default/8.flash_ctrl_phy_arb.4078164418 |
|
|
Jun 24 07:25:46 PM PDT 24 |
Jun 24 07:32:33 PM PDT 24 |
8894194100 ps |
| T1103 |
/workspace/coverage/default/1.flash_ctrl_alert_test.2777164492 |
|
|
Jun 24 07:18:33 PM PDT 24 |
Jun 24 07:18:49 PM PDT 24 |
18466600 ps |
| T1104 |
/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.2304297059 |
|
|
Jun 24 07:33:44 PM PDT 24 |
Jun 24 07:39:14 PM PDT 24 |
12567733100 ps |
| T1105 |
/workspace/coverage/default/4.flash_ctrl_config_regwen.441582523 |
|
|
Jun 24 07:23:13 PM PDT 24 |
Jun 24 07:23:29 PM PDT 24 |
60046700 ps |
| T1106 |
/workspace/coverage/default/26.flash_ctrl_sec_info_access.3664997378 |
|
|
Jun 24 07:33:13 PM PDT 24 |
Jun 24 07:34:30 PM PDT 24 |
755258600 ps |
| T1107 |
/workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.2796364791 |
|
|
Jun 24 07:26:48 PM PDT 24 |
Jun 24 07:27:12 PM PDT 24 |
15818200 ps |
| T1108 |
/workspace/coverage/default/22.flash_ctrl_smoke.2275886554 |
|
|
Jun 24 07:31:19 PM PDT 24 |
Jun 24 07:33:05 PM PDT 24 |
113394000 ps |
| T1109 |
/workspace/coverage/default/1.flash_ctrl_derr_detect.2866681871 |
|
|
Jun 24 07:17:46 PM PDT 24 |
Jun 24 07:19:34 PM PDT 24 |
186544000 ps |
| T1110 |
/workspace/coverage/default/13.flash_ctrl_intr_rd.3764703204 |
|
|
Jun 24 07:28:36 PM PDT 24 |
Jun 24 07:30:55 PM PDT 24 |
890512600 ps |
| T1111 |
/workspace/coverage/default/6.flash_ctrl_ro_derr.1876481854 |
|
|
Jun 24 07:24:15 PM PDT 24 |
Jun 24 07:27:02 PM PDT 24 |
11946770700 ps |
| T1112 |
/workspace/coverage/default/19.flash_ctrl_prog_reset.2380450564 |
|
|
Jun 24 07:30:56 PM PDT 24 |
Jun 24 07:31:11 PM PDT 24 |
18040900 ps |
| T1113 |
/workspace/coverage/default/14.flash_ctrl_connect.651806249 |
|
|
Jun 24 07:28:50 PM PDT 24 |
Jun 24 07:29:08 PM PDT 24 |
35795300 ps |
| T1114 |
/workspace/coverage/default/30.flash_ctrl_disable.382869365 |
|
|
Jun 24 07:32:35 PM PDT 24 |
Jun 24 07:32:58 PM PDT 24 |
10256500 ps |
| T1115 |
/workspace/coverage/default/11.flash_ctrl_connect.1505387299 |
|
|
Jun 24 07:27:57 PM PDT 24 |
Jun 24 07:28:16 PM PDT 24 |
17985100 ps |
| T69 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3902515967 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 07:06:55 PM PDT 24 |
1424451800 ps |
| T70 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2502012087 |
|
|
Jun 24 06:58:23 PM PDT 24 |
Jun 24 07:14:01 PM PDT 24 |
2588215700 ps |
| T264 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1519244389 |
|
|
Jun 24 06:59:10 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
43748100 ps |
| T1116 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1648291818 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:18 PM PDT 24 |
14714800 ps |
| T71 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2268743570 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 06:59:09 PM PDT 24 |
85975500 ps |
| T265 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3893458181 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
67555800 ps |
| T111 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2047475131 |
|
|
Jun 24 06:58:43 PM PDT 24 |
Jun 24 06:59:32 PM PDT 24 |
48928400 ps |
| T319 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2584999093 |
|
|
Jun 24 06:59:06 PM PDT 24 |
Jun 24 06:59:43 PM PDT 24 |
15733600 ps |
| T248 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1408461256 |
|
|
Jun 24 06:58:03 PM PDT 24 |
Jun 24 06:58:51 PM PDT 24 |
257708800 ps |
| T320 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3370940284 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 06:59:17 PM PDT 24 |
24432000 ps |
| T1117 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3156587303 |
|
|
Jun 24 06:57:52 PM PDT 24 |
Jun 24 06:58:29 PM PDT 24 |
12461300 ps |
| T249 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2960319860 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 06:59:36 PM PDT 24 |
416659800 ps |
| T1118 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2747738897 |
|
|
Jun 24 06:58:15 PM PDT 24 |
Jun 24 06:58:59 PM PDT 24 |
13369200 ps |
| T211 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1174517304 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:21 PM PDT 24 |
69144900 ps |
| T250 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.63124499 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:22 PM PDT 24 |
110929400 ps |
| T1119 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1692941049 |
|
|
Jun 24 06:58:33 PM PDT 24 |
Jun 24 06:59:21 PM PDT 24 |
21172300 ps |
| T1120 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.389624249 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:13 PM PDT 24 |
55550000 ps |
| T212 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3304827262 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:16 PM PDT 24 |
236008900 ps |
| T224 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3274029156 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:20 PM PDT 24 |
66619800 ps |
| T251 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1767084303 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:34 PM PDT 24 |
338104000 ps |
| T225 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2486158426 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 07:06:53 PM PDT 24 |
370756000 ps |
| T322 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1791899595 |
|
|
Jun 24 06:59:07 PM PDT 24 |
Jun 24 06:59:45 PM PDT 24 |
27117800 ps |
| T323 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2077237161 |
|
|
Jun 24 06:59:08 PM PDT 24 |
Jun 24 06:59:45 PM PDT 24 |
17675100 ps |
| T226 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2497605788 |
|
|
Jun 24 06:58:33 PM PDT 24 |
Jun 24 06:59:21 PM PDT 24 |
322049200 ps |
| T227 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1665668192 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 06:59:23 PM PDT 24 |
567188800 ps |
| T1121 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3987299758 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:16 PM PDT 24 |
12924300 ps |
| T321 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1888903509 |
|
|
Jun 24 06:58:46 PM PDT 24 |
Jun 24 06:59:31 PM PDT 24 |
38926600 ps |
| T343 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1984335216 |
|
|
Jun 24 06:59:06 PM PDT 24 |
Jun 24 06:59:45 PM PDT 24 |
16574000 ps |
| T228 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2219966315 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:58:41 PM PDT 24 |
57534900 ps |
| T229 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1655056055 |
|
|
Jun 24 06:58:25 PM PDT 24 |
Jun 24 06:59:16 PM PDT 24 |
305333900 ps |
| T230 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3204555109 |
|
|
Jun 24 06:57:51 PM PDT 24 |
Jun 24 06:58:33 PM PDT 24 |
117728800 ps |
| T324 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.154196744 |
|
|
Jun 24 06:58:46 PM PDT 24 |
Jun 24 06:59:31 PM PDT 24 |
16898400 ps |
| T252 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1710987827 |
|
|
Jun 24 06:57:54 PM PDT 24 |
Jun 24 06:58:37 PM PDT 24 |
125015900 ps |
| T325 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1280974444 |
|
|
Jun 24 06:58:44 PM PDT 24 |
Jun 24 06:59:28 PM PDT 24 |
28353500 ps |
| T253 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2073210822 |
|
|
Jun 24 06:58:43 PM PDT 24 |
Jun 24 06:59:35 PM PDT 24 |
196129100 ps |
| T231 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4090559917 |
|
|
Jun 24 06:57:54 PM PDT 24 |
Jun 24 06:58:37 PM PDT 24 |
47657300 ps |
| T254 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.690843996 |
|
|
Jun 24 06:58:25 PM PDT 24 |
Jun 24 06:59:15 PM PDT 24 |
155640500 ps |
| T360 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3417666390 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:23 PM PDT 24 |
47916800 ps |
| T262 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.115159607 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 06:59:24 PM PDT 24 |
360056600 ps |
| T359 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.163871790 |
|
|
Jun 24 06:58:27 PM PDT 24 |
Jun 24 06:59:16 PM PDT 24 |
143712500 ps |
| T1122 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2824873138 |
|
|
Jun 24 06:58:44 PM PDT 24 |
Jun 24 06:59:29 PM PDT 24 |
80516700 ps |
| T1123 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1241394156 |
|
|
Jun 24 06:58:42 PM PDT 24 |
Jun 24 06:59:28 PM PDT 24 |
14422200 ps |
| T293 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.129784064 |
|
|
Jun 24 06:58:47 PM PDT 24 |
Jun 24 06:59:54 PM PDT 24 |
397222000 ps |
| T1124 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3723052830 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
398709900 ps |
| T1125 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2278173746 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
15507600 ps |
| T1126 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2688752552 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
20949100 ps |
| T1127 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3942120416 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 06:59:21 PM PDT 24 |
31790000 ps |
| T266 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1473139001 |
|
|
Jun 24 06:58:44 PM PDT 24 |
Jun 24 07:07:01 PM PDT 24 |
813743800 ps |
| T261 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.896338628 |
|
|
Jun 24 06:58:43 PM PDT 24 |
Jun 24 06:59:33 PM PDT 24 |
100306300 ps |
| T326 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.128757524 |
|
|
Jun 24 06:59:09 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
30233900 ps |
| T1128 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.869573273 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:17 PM PDT 24 |
17843700 ps |
| T1129 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1633955066 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:20 PM PDT 24 |
28344500 ps |
| T1130 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2383786817 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:21 PM PDT 24 |
70948600 ps |
| T1131 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2716861387 |
|
|
Jun 24 06:58:22 PM PDT 24 |
Jun 24 06:59:10 PM PDT 24 |
23443300 ps |
| T1132 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2128187845 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:58:38 PM PDT 24 |
47520200 ps |
| T345 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4024277761 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 07:11:36 PM PDT 24 |
680592100 ps |
| T1133 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2111924071 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
12040900 ps |
| T1134 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.842463908 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
166646400 ps |
| T1135 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1546403457 |
|
|
Jun 24 06:59:07 PM PDT 24 |
Jun 24 06:59:45 PM PDT 24 |
27119800 ps |
| T1136 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.400164988 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
133236400 ps |
| T263 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.286130681 |
|
|
Jun 24 06:58:24 PM PDT 24 |
Jun 24 06:59:13 PM PDT 24 |
88247500 ps |
| T269 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2094153804 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
27555400 ps |
| T1137 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.119782618 |
|
|
Jun 24 06:58:20 PM PDT 24 |
Jun 24 06:59:07 PM PDT 24 |
65909300 ps |
| T350 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3931752008 |
|
|
Jun 24 06:57:48 PM PDT 24 |
Jun 24 07:10:35 PM PDT 24 |
695756500 ps |
| T1138 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1594500283 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:15 PM PDT 24 |
33564900 ps |
| T1139 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3804550363 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
42504900 ps |
| T1140 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.20439382 |
|
|
Jun 24 06:58:22 PM PDT 24 |
Jun 24 06:59:06 PM PDT 24 |
70459500 ps |
| T1141 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.495611718 |
|
|
Jun 24 06:57:54 PM PDT 24 |
Jun 24 06:58:36 PM PDT 24 |
12417300 ps |
| T1142 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1567319569 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:58:39 PM PDT 24 |
38274800 ps |
| T267 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4156982610 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:21 PM PDT 24 |
48624100 ps |
| T351 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.438794087 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 07:13:31 PM PDT 24 |
1170850300 ps |
| T1143 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1955891431 |
|
|
Jun 24 06:57:54 PM PDT 24 |
Jun 24 06:58:34 PM PDT 24 |
30496200 ps |
| T1144 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1088344036 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:13 PM PDT 24 |
99221300 ps |
| T1145 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3210657658 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 06:58:42 PM PDT 24 |
60266100 ps |
| T1146 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3806254840 |
|
|
Jun 24 06:57:50 PM PDT 24 |
Jun 24 06:58:46 PM PDT 24 |
1800770800 ps |
| T1147 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1908500707 |
|
|
Jun 24 06:58:26 PM PDT 24 |
Jun 24 06:59:13 PM PDT 24 |
12872600 ps |
| T1148 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1069512226 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:16 PM PDT 24 |
20954400 ps |
| T344 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1544026424 |
|
|
Jun 24 06:58:24 PM PDT 24 |
Jun 24 06:59:14 PM PDT 24 |
100214100 ps |
| T1149 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2550957660 |
|
|
Jun 24 06:58:33 PM PDT 24 |
Jun 24 06:59:22 PM PDT 24 |
94858000 ps |
| T1150 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1105022792 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 06:58:36 PM PDT 24 |
58559900 ps |
| T1151 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.70140412 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:20 PM PDT 24 |
80621600 ps |
| T1152 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2429137798 |
|
|
Jun 24 06:59:08 PM PDT 24 |
Jun 24 06:59:45 PM PDT 24 |
17775300 ps |
| T1153 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3344937966 |
|
|
Jun 24 06:57:57 PM PDT 24 |
Jun 24 06:58:41 PM PDT 24 |
25152200 ps |
| T1154 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2417060805 |
|
|
Jun 24 06:58:42 PM PDT 24 |
Jun 24 06:59:27 PM PDT 24 |
26301100 ps |
| T1155 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.148894974 |
|
|
Jun 24 06:59:10 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
55227300 ps |
| T294 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.316925049 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:18 PM PDT 24 |
154728400 ps |
| T1156 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2333280572 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:58:39 PM PDT 24 |
53050700 ps |
| T1157 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1766554558 |
|
|
Jun 24 06:58:25 PM PDT 24 |
Jun 24 06:59:12 PM PDT 24 |
34038000 ps |
| T1158 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2317979636 |
|
|
Jun 24 06:58:23 PM PDT 24 |
Jun 24 06:59:09 PM PDT 24 |
48182600 ps |
| T295 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3636631649 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:41 PM PDT 24 |
251281600 ps |
| T1159 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.2991081194 |
|
|
Jun 24 06:57:53 PM PDT 24 |
Jun 24 06:58:31 PM PDT 24 |
66409900 ps |
| T1160 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2544868511 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:59:06 PM PDT 24 |
1554910100 ps |
| T1161 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3611380036 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
19254600 ps |
| T1162 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4165681534 |
|
|
Jun 24 06:58:33 PM PDT 24 |
Jun 24 06:59:22 PM PDT 24 |
72085800 ps |
| T296 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1520934055 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:20 PM PDT 24 |
385010200 ps |
| T1163 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.811902010 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 06:59:21 PM PDT 24 |
12784300 ps |
| T1164 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.814384100 |
|
|
Jun 24 06:57:53 PM PDT 24 |
Jun 24 06:58:32 PM PDT 24 |
85650200 ps |
| T297 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1090118985 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:16 PM PDT 24 |
77389200 ps |
| T268 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3169664054 |
|
|
Jun 24 06:57:57 PM PDT 24 |
Jun 24 06:58:42 PM PDT 24 |
67600900 ps |
| T1165 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3942937498 |
|
|
Jun 24 06:58:22 PM PDT 24 |
Jun 24 06:59:08 PM PDT 24 |
31396200 ps |
| T1166 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3212752084 |
|
|
Jun 24 06:57:57 PM PDT 24 |
Jun 24 06:58:39 PM PDT 24 |
31884000 ps |
| T233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1647600053 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 06:58:36 PM PDT 24 |
22419900 ps |
| T298 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1226122814 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:21 PM PDT 24 |
444380500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3965409409 |
|
|
Jun 24 06:59:10 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
18301600 ps |
| T299 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1879236305 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 07:14:20 PM PDT 24 |
2880327700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.4126407802 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:58:40 PM PDT 24 |
21987800 ps |
| T346 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1345558919 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 07:14:23 PM PDT 24 |
721707900 ps |
| T1169 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1346663890 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:13 PM PDT 24 |
51723800 ps |
| T1170 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.580755750 |
|
|
Jun 24 06:58:15 PM PDT 24 |
Jun 24 06:59:01 PM PDT 24 |
28300200 ps |
| T1171 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.368135611 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 06:58:41 PM PDT 24 |
40238100 ps |
| T1172 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.78414851 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
2739605400 ps |
| T1173 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1329621602 |
|
|
Jun 24 06:58:43 PM PDT 24 |
Jun 24 06:59:30 PM PDT 24 |
27786100 ps |
| T234 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1924433361 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:58:39 PM PDT 24 |
223425400 ps |
| T300 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3463596792 |
|
|
Jun 24 06:57:49 PM PDT 24 |
Jun 24 06:58:19 PM PDT 24 |
232040000 ps |
| T1174 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4189425884 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:41 PM PDT 24 |
48606900 ps |
| T1175 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2991710412 |
|
|
Jun 24 06:58:25 PM PDT 24 |
Jun 24 06:59:54 PM PDT 24 |
1288952100 ps |
| T1176 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3555455767 |
|
|
Jun 24 06:57:52 PM PDT 24 |
Jun 24 06:58:35 PM PDT 24 |
108086700 ps |
| T1177 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3892088336 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:35 PM PDT 24 |
789253900 ps |
| T1178 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2720828177 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
22286400 ps |
| T235 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.426813190 |
|
|
Jun 24 06:57:54 PM PDT 24 |
Jun 24 06:58:34 PM PDT 24 |
17097800 ps |
| T270 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.325633480 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 06:59:24 PM PDT 24 |
68012700 ps |
| T1179 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.752341459 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:18 PM PDT 24 |
588289700 ps |
| T301 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3412845250 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 07:14:10 PM PDT 24 |
822749300 ps |
| T1180 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3237238522 |
|
|
Jun 24 06:59:05 PM PDT 24 |
Jun 24 06:59:42 PM PDT 24 |
15886600 ps |
| T1181 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.328157900 |
|
|
Jun 24 06:57:50 PM PDT 24 |
Jun 24 06:58:17 PM PDT 24 |
21240400 ps |
| T1182 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1735235525 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 06:59:21 PM PDT 24 |
12879300 ps |
| T1183 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4030651522 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:58:41 PM PDT 24 |
14432800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2385783374 |
|
|
Jun 24 06:58:43 PM PDT 24 |
Jun 24 06:59:31 PM PDT 24 |
43600600 ps |
| T352 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3791770920 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 07:06:50 PM PDT 24 |
224817200 ps |
| T1185 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1812476397 |
|
|
Jun 24 06:59:12 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
17554600 ps |
| T1186 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3215507711 |
|
|
Jun 24 06:59:09 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
24877400 ps |
| T1187 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2499051062 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 06:59:22 PM PDT 24 |
68996000 ps |
| T1188 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3393321349 |
|
|
Jun 24 06:59:09 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
100510800 ps |
| T1189 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.215242489 |
|
|
Jun 24 06:59:12 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
87267400 ps |
| T353 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3417564498 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 07:14:15 PM PDT 24 |
673460200 ps |
| T302 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2084912982 |
|
|
Jun 24 06:57:51 PM PDT 24 |
Jun 24 06:58:34 PM PDT 24 |
103889700 ps |
| T303 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4209786344 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 06:59:20 PM PDT 24 |
258453900 ps |
| T1190 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.4095320039 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 06:58:36 PM PDT 24 |
19595400 ps |
| T1191 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1444499506 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:15 PM PDT 24 |
14371600 ps |
| T1192 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2421807556 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
28483000 ps |
| T1193 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.204686239 |
|
|
Jun 24 06:59:12 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
51146100 ps |
| T1194 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.294831872 |
|
|
Jun 24 06:57:54 PM PDT 24 |
Jun 24 07:06:14 PM PDT 24 |
1682402900 ps |
| T1195 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1834487469 |
|
|
Jun 24 06:58:23 PM PDT 24 |
Jun 24 06:59:12 PM PDT 24 |
202539700 ps |
| T1196 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.184782818 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
30153500 ps |
| T1197 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3965976099 |
|
|
Jun 24 06:57:58 PM PDT 24 |
Jun 24 06:59:56 PM PDT 24 |
18209729400 ps |
| T1198 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2433988492 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
37297900 ps |
| T1199 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.69629827 |
|
|
Jun 24 06:57:53 PM PDT 24 |
Jun 24 06:59:04 PM PDT 24 |
27540400 ps |
| T354 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.599908129 |
|
|
Jun 24 06:58:33 PM PDT 24 |
Jun 24 07:05:27 PM PDT 24 |
671246000 ps |
| T1200 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3497521391 |
|
|
Jun 24 06:59:09 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
17651700 ps |
| T1201 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1120649349 |
|
|
Jun 24 06:58:44 PM PDT 24 |
Jun 24 06:59:35 PM PDT 24 |
730474600 ps |
| T1202 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1653580570 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:15 PM PDT 24 |
135834800 ps |
| T304 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1942249989 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:16 PM PDT 24 |
107462200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.398916819 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:18 PM PDT 24 |
32200200 ps |
| T1204 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.420656478 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 06:59:21 PM PDT 24 |
156986100 ps |
| T1205 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1133600346 |
|
|
Jun 24 06:59:07 PM PDT 24 |
Jun 24 06:59:45 PM PDT 24 |
53585400 ps |
| T1206 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2657583823 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:12 PM PDT 24 |
24305100 ps |
| T1207 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.384700130 |
|
|
Jun 24 06:57:52 PM PDT 24 |
Jun 24 06:58:48 PM PDT 24 |
222352000 ps |
| T1208 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3396700595 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:58:39 PM PDT 24 |
102121300 ps |
| T1209 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3058642594 |
|
|
Jun 24 06:58:27 PM PDT 24 |
Jun 24 06:59:53 PM PDT 24 |
667572200 ps |
| T347 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2971793603 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 07:14:16 PM PDT 24 |
1977980100 ps |
| T236 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4067480461 |
|
|
Jun 24 06:57:52 PM PDT 24 |
Jun 24 06:58:27 PM PDT 24 |
16867800 ps |
| T1210 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3576607621 |
|
|
Jun 24 06:58:34 PM PDT 24 |
Jun 24 06:59:23 PM PDT 24 |
50653800 ps |
| T271 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3179300365 |
|
|
Jun 24 06:58:26 PM PDT 24 |
Jun 24 06:59:17 PM PDT 24 |
58447900 ps |
| T1211 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2142577583 |
|
|
Jun 24 06:58:43 PM PDT 24 |
Jun 24 06:59:31 PM PDT 24 |
17925400 ps |
| T349 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.277117043 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 07:11:41 PM PDT 24 |
1355010700 ps |
| T1212 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.129178987 |
|
|
Jun 24 06:57:54 PM PDT 24 |
Jun 24 06:58:33 PM PDT 24 |
20868500 ps |
| T1213 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.210576302 |
|
|
Jun 24 06:58:23 PM PDT 24 |
Jun 24 06:59:12 PM PDT 24 |
107768500 ps |
| T1214 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1090842364 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:58:38 PM PDT 24 |
16362500 ps |
| T1215 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2149203785 |
|
|
Jun 24 06:58:46 PM PDT 24 |
Jun 24 06:59:36 PM PDT 24 |
641096900 ps |
| T1216 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3607331822 |
|
|
Jun 24 06:57:57 PM PDT 24 |
Jun 24 06:58:41 PM PDT 24 |
61048800 ps |
| T305 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1725705441 |
|
|
Jun 24 06:57:57 PM PDT 24 |
Jun 24 06:59:12 PM PDT 24 |
49428900 ps |
| T1217 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1055321943 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
92287400 ps |
| T1218 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.289221420 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 06:58:39 PM PDT 24 |
65096800 ps |
| T1219 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3658418122 |
|
|
Jun 24 06:59:08 PM PDT 24 |
Jun 24 06:59:45 PM PDT 24 |
27556400 ps |
| T1220 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1295828624 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:15 PM PDT 24 |
18382100 ps |
| T1221 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2521663533 |
|
|
Jun 24 06:58:43 PM PDT 24 |
Jun 24 06:59:28 PM PDT 24 |
56709900 ps |
| T306 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1308584808 |
|
|
Jun 24 06:58:20 PM PDT 24 |
Jun 24 06:59:24 PM PDT 24 |
227219500 ps |
| T1222 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3228396202 |
|
|
Jun 24 06:57:51 PM PDT 24 |
Jun 24 06:58:25 PM PDT 24 |
67727100 ps |
| T1223 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1901291428 |
|
|
Jun 24 06:57:54 PM PDT 24 |
Jun 24 06:58:53 PM PDT 24 |
472859700 ps |
| T1224 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2719134111 |
|
|
Jun 24 06:57:52 PM PDT 24 |
Jun 24 06:58:29 PM PDT 24 |
15069000 ps |
| T356 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1441708353 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 07:05:35 PM PDT 24 |
755729200 ps |
| T1225 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.264160437 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
37890600 ps |
| T1226 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3577992645 |
|
|
Jun 24 06:57:51 PM PDT 24 |
Jun 24 06:58:26 PM PDT 24 |
51280000 ps |
| T1227 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.7774021 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 07:06:06 PM PDT 24 |
1357123900 ps |
| T1228 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1387558692 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:15 PM PDT 24 |
25286800 ps |
| T1229 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1601906848 |
|
|
Jun 24 06:58:33 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
15817200 ps |
| T348 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.4187030504 |
|
|
Jun 24 06:57:52 PM PDT 24 |
Jun 24 07:05:55 PM PDT 24 |
172082000 ps |
| T237 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2361786733 |
|
|
Jun 24 06:58:23 PM PDT 24 |
Jun 24 06:59:08 PM PDT 24 |
116357100 ps |
| T1230 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2381032323 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 06:59:02 PM PDT 24 |
1340253500 ps |
| T1231 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.885585461 |
|
|
Jun 24 06:59:09 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
18279300 ps |
| T1232 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2015730242 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 06:58:40 PM PDT 24 |
24894600 ps |
| T1233 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1290682950 |
|
|
Jun 24 06:58:23 PM PDT 24 |
Jun 24 06:59:13 PM PDT 24 |
568033800 ps |
| T1234 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1151139095 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
13926200 ps |
| T1235 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1289034815 |
|
|
Jun 24 06:58:43 PM PDT 24 |
Jun 24 06:59:28 PM PDT 24 |
17207300 ps |
| T1236 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1161039478 |
|
|
Jun 24 06:58:30 PM PDT 24 |
Jun 24 06:59:21 PM PDT 24 |
139876100 ps |
| T1237 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3689727504 |
|
|
Jun 24 06:58:31 PM PDT 24 |
Jun 24 06:59:23 PM PDT 24 |
205055300 ps |
| T1238 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2662145997 |
|
|
Jun 24 06:57:56 PM PDT 24 |
Jun 24 06:59:51 PM PDT 24 |
6280785500 ps |
| T1239 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1074017926 |
|
|
Jun 24 06:58:44 PM PDT 24 |
Jun 24 06:59:28 PM PDT 24 |
16365000 ps |
| T1240 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.630496522 |
|
|
Jun 24 06:59:08 PM PDT 24 |
Jun 24 06:59:45 PM PDT 24 |
27991000 ps |
| T1241 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3672367824 |
|
|
Jun 24 06:57:54 PM PDT 24 |
Jun 24 06:58:31 PM PDT 24 |
17424200 ps |
| T1242 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4121794530 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 06:58:38 PM PDT 24 |
74141500 ps |
| T1243 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1714504258 |
|
|
Jun 24 06:57:55 PM PDT 24 |
Jun 24 06:58:57 PM PDT 24 |
158459500 ps |
| T1244 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2013723399 |
|
|
Jun 24 06:58:32 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
58775300 ps |
| T1245 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1834179897 |
|
|
Jun 24 06:58:28 PM PDT 24 |
Jun 24 06:59:20 PM PDT 24 |
1119943300 ps |
| T1246 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.164379821 |
|
|
Jun 24 06:58:04 PM PDT 24 |
Jun 24 06:58:51 PM PDT 24 |
139662300 ps |
| T1247 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.117412208 |
|
|
Jun 24 06:58:33 PM PDT 24 |
Jun 24 06:59:19 PM PDT 24 |
16053300 ps |
| T1248 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1107339522 |
|
|
Jun 24 06:58:29 PM PDT 24 |
Jun 24 06:59:16 PM PDT 24 |
72240200 ps |
| T1249 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.451698350 |
|
|
Jun 24 06:58:26 PM PDT 24 |
Jun 24 06:59:13 PM PDT 24 |
62038100 ps |
| T1250 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1093914455 |
|
|
Jun 24 06:59:06 PM PDT 24 |
Jun 24 06:59:45 PM PDT 24 |
29773900 ps |
| T1251 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.171696656 |
|
|
Jun 24 06:59:12 PM PDT 24 |
Jun 24 06:59:46 PM PDT 24 |
42755800 ps |