Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20131	1		T59	91		T95	798		T60	9
full_word	3868234	1		T2	16245		T3	40766		T5	15027

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3888097	1		T2	16245		T3	40766		T5	15027
auto[TlIntgErrCmd]	91	1		T60	4		T96	4		T216	3
auto[TlIntgErrData]	80	1		T60	3		T96	1		T216	2
auto[TlIntgErrBoth]	97	1		T60	2		T96	4		T216	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3862674	1		T2	16245		T3	40766		T5	15027
auto[1]	25691	1		T59	113		T95	1124		T60	6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1273	1		T59	10		T95	43		T203	28
auto[TlIntgErrNone]	partial	auto[1]	18609	1		T59	81		T95	755		T203	943
auto[TlIntgErrNone]	full_word	auto[0]	3861292	1		T2	16245		T3	40766		T5	15027
auto[TlIntgErrNone]	full_word	auto[1]	6923	1		T59	32		T95	369		T203	318
auto[TlIntgErrCmd]	partial	auto[0]	31	1		T60	1		T96	3		T246	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T60	3		T96	1		T216	3
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T240	1		T242	1		T345	1
auto[TlIntgErrData]	partial	auto[0]	38	1		T60	1		T216	1		T246	2
auto[TlIntgErrData]	partial	auto[1]	35	1		T60	2		T96	1		T216	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T240	1		T348	1		T243	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T349	1		T350	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T60	1		T96	1		T216	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T60	1		T96	2		T216	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T242	1		T348	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T96	1		T240	1		T242	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26267255	1		T1	22913		T2	11845		T3	186066
full_word	7564311	1		T1	12712		T2	8644		T3	29852

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33831276	1		T1	35625		T2	20489		T3	215918
auto[TlIntgErrCmd]	87	1		T60	2		T96	5		T216	4
auto[TlIntgErrData]	112	1		T60	4		T96	2		T216	6
auto[TlIntgErrBoth]	91	1		T60	4		T96	3		T246	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29419705	1		T1	26125		T2	17446		T3	194111
auto[1]	4411861	1		T1	9500		T2	3043		T3	21807

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25570396	1		T1	21702		T2	10987		T3	183278
auto[TlIntgErrNone]	partial	auto[1]	696590	1		T1	1211		T2	858		T3	2788
auto[TlIntgErrNone]	full_word	auto[0]	3849174	1		T1	4423		T2	6459		T3	10833
auto[TlIntgErrNone]	full_word	auto[1]	3715116	1		T1	8289		T2	2185		T3	19019
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T60	1		T96	2		T216	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T60	1		T96	3		T216	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T234	1		T346	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T240	1		T243	1		T351	1
auto[TlIntgErrData]	partial	auto[0]	50	1		T60	3		T96	1		T216	2
auto[TlIntgErrData]	partial	auto[1]	53	1		T60	1		T96	1		T216	4
auto[TlIntgErrData]	full_word	auto[0]	4	1		T236	2		T243	1		T350	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T242	2		T348	1		T351	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T246	5		T257	2		T236	1
auto[TlIntgErrBoth]	partial	auto[1]	41	1		T60	3		T96	3		T246	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T348	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T60	1		T348	1		T351	1