Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1518407712	1515204060	0	0
CheckNGreaterZero_A	4156	4156	0	0
GntImpliesReady_A	1518407712	409785882	0	0
GntImpliesValid_A	1518407712	409785882	0	0
GrantKnown_A	1518407712	1515204060	0	0
IdxKnown_A	1518407712	1515204060	0	0
IndexIsCorrect_A	1518407712	409785882	0	0
NoReadyValidNoGrant_A	1518407712	179480939	0	0
Priority_A	1518407712	433148907	0	0
ReadyAndValidImplyGrant_A	1518407712	409785882	0	0
ReqAndReadyImplyGrant_A	1518407712	409785882	0	0
ReqImpliesValid_A	1518407712	433148907	0	0
ValidKnown_A	1518407712	1515204060	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	1515204060	0	0
T1	1089300	1039112	0	0
T2	201448	201064	0	0
T3	1756592	1756264	0	0
T4	10260	9912	0	0
T5	208668	208372	0	0
T14	9548	9212	0	0
T15	188724	188176	0	0
T16	5128	4880	0	0
T17	562508	562140	0	0
T18	464008	463724	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4156	4156	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	409785882	0	0
T1	544650	232606	0	0
T2	201448	44194	0	0
T3	1756592	592066	0	0
T4	10260	724	0	0
T5	208668	38492	0	0
T10	0	132	0	0
T14	9548	64	0	0
T15	188724	42712	0	0
T16	5128	64	0	0
T17	562508	3656	0	0
T18	464008	584	0	0
T20	0	130008	0	0
T24	0	15852	0	0
T29	126492	0	0	0
T42	0	122676	0	0
T52	0	18850	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	409785882	0	0
T1	544650	232606	0	0
T2	201448	44194	0	0
T3	1756592	592066	0	0
T4	10260	724	0	0
T5	208668	38492	0	0
T10	0	132	0	0
T14	9548	64	0	0
T15	188724	42712	0	0
T16	5128	64	0	0
T17	562508	3656	0	0
T18	464008	584	0	0
T20	0	130008	0	0
T24	0	15852	0	0
T29	126492	0	0	0
T42	0	122676	0	0
T52	0	18850	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	1515204060	0	0
T1	1089300	1039112	0	0
T2	201448	201064	0	0
T3	1756592	1756264	0	0
T4	10260	9912	0	0
T5	208668	208372	0	0
T14	9548	9212	0	0
T15	188724	188176	0	0
T16	5128	4880	0	0
T17	562508	562140	0	0
T18	464008	463724	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	1515204060	0	0
T1	1089300	1039112	0	0
T2	201448	201064	0	0
T3	1756592	1756264	0	0
T4	10260	9912	0	0
T5	208668	208372	0	0
T14	9548	9212	0	0
T15	188724	188176	0	0
T16	5128	4880	0	0
T17	562508	562140	0	0
T18	464008	463724	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	409785882	0	0
T1	544650	232606	0	0
T2	201448	44194	0	0
T3	1756592	592066	0	0
T4	10260	724	0	0
T5	208668	38492	0	0
T10	0	132	0	0
T14	9548	64	0	0
T15	188724	42712	0	0
T16	5128	64	0	0
T17	562508	3656	0	0
T18	464008	584	0	0
T20	0	130008	0	0
T24	0	15852	0	0
T29	126492	0	0	0
T42	0	122676	0	0
T52	0	18850	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	179480939	0	0
T1	544650	61880	0	0
T2	201448	55740	0	0
T3	1756592	196608	0	0
T4	10260	318	0	0
T5	208668	111554	0	0
T14	9548	256	0	0
T15	188724	76164	0	0
T16	5128	256	0	0
T17	562508	5760	0	0
T18	464008	128	0	0
T20	0	83506	0	0
T22	0	32	0	0
T23	0	42	0	0
T24	0	567342	0	0
T25	0	44	0	0
T29	126492	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	433148907	0	0
T1	544650	232606	0	0
T2	201448	72750	0	0
T3	1756592	713810	0	0
T4	10260	724	0	0
T5	208668	40546	0	0
T10	0	132	0	0
T14	9548	64	0	0
T15	188724	52368	0	0
T16	5128	64	0	0
T17	562508	3656	0	0
T18	464008	584	0	0
T20	0	153030	0	0
T24	0	250254	0	0
T29	126492	0	0	0
T42	0	122676	0	0
T52	0	18850	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	409785882	0	0
T1	544650	232606	0	0
T2	201448	44194	0	0
T3	1756592	592066	0	0
T4	10260	724	0	0
T5	208668	38492	0	0
T10	0	132	0	0
T14	9548	64	0	0
T15	188724	42712	0	0
T16	5128	64	0	0
T17	562508	3656	0	0
T18	464008	584	0	0
T20	0	130008	0	0
T24	0	15852	0	0
T29	126492	0	0	0
T42	0	122676	0	0
T52	0	18850	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	409785882	0	0
T1	544650	232606	0	0
T2	201448	44194	0	0
T3	1756592	592066	0	0
T4	10260	724	0	0
T5	208668	38492	0	0
T10	0	132	0	0
T14	9548	64	0	0
T15	188724	42712	0	0
T16	5128	64	0	0
T17	562508	3656	0	0
T18	464008	584	0	0
T20	0	130008	0	0
T24	0	15852	0	0
T29	126492	0	0	0
T42	0	122676	0	0
T52	0	18850	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	433148907	0	0
T1	544650	232606	0	0
T2	201448	72750	0	0
T3	1756592	713810	0	0
T4	10260	724	0	0
T5	208668	40546	0	0
T10	0	132	0	0
T14	9548	64	0	0
T15	188724	52368	0	0
T16	5128	64	0	0
T17	562508	3656	0	0
T18	464008	584	0	0
T20	0	153030	0	0
T24	0	250254	0	0
T29	126492	0	0	0
T42	0	122676	0	0
T52	0	18850	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1518407712	1515204060	0	0
T1	1089300	1039112	0	0
T2	201448	201064	0	0
T3	1756592	1756264	0	0
T4	10260	9912	0	0
T5	208668	208372	0	0
T14	9548	9212	0	0
T15	188724	188176	0	0
T16	5128	4880	0	0
T17	562508	562140	0	0
T18	464008	463724	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	379601928	378801015	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	379601928	104530522	0	0
GntImpliesValid_A	379601928	104530522	0	0
GrantKnown_A	379601928	378801015	0	0
IdxKnown_A	379601928	378801015	0	0
IndexIsCorrect_A	379601928	104530522	0	0
NoReadyValidNoGrant_A	379601928	45933675	0	0
Priority_A	379601928	110353301	0	0
ReadyAndValidImplyGrant_A	379601928	104530522	0	0
ReqAndReadyImplyGrant_A	379601928	104530522	0	0
ReqImpliesValid_A	379601928	110353301	0	0
ValidKnown_A	379601928	378801015	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	104530522	0	0
T1	272325	116303	0	0
T2	50362	11516	0	0
T3	439148	170043	0	0
T4	2565	45	0	0
T5	52167	8967	0	0
T14	2387	32	0	0
T15	47181	13313	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	104530522	0	0
T1	272325	116303	0	0
T2	50362	11516	0	0
T3	439148	170043	0	0
T4	2565	45	0	0
T5	52167	8967	0	0
T14	2387	32	0	0
T15	47181	13313	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	104530522	0	0
T1	272325	116303	0	0
T2	50362	11516	0	0
T3	439148	170043	0	0
T4	2565	45	0	0
T5	52167	8967	0	0
T14	2387	32	0	0
T15	47181	13313	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	45933675	0	0
T1	272325	30940	0	0
T2	50362	15334	0	0
T3	439148	55075	0	0
T4	2565	148	0	0
T5	52167	26887	0	0
T14	2387	128	0	0
T15	47181	24391	0	0
T16	1282	128	0	0
T17	140627	2880	0	0
T18	116002	64	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	110353301	0	0
T1	272325	116303	0	0
T2	50362	18290	0	0
T3	439148	204724	0	0
T4	2565	45	0	0
T5	52167	9394	0	0
T14	2387	32	0	0
T15	47181	16431	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	104530522	0	0
T1	272325	116303	0	0
T2	50362	11516	0	0
T3	439148	170043	0	0
T4	2565	45	0	0
T5	52167	8967	0	0
T14	2387	32	0	0
T15	47181	13313	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	104530522	0	0
T1	272325	116303	0	0
T2	50362	11516	0	0
T3	439148	170043	0	0
T4	2565	45	0	0
T5	52167	8967	0	0
T14	2387	32	0	0
T15	47181	13313	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	110353301	0	0
T1	272325	116303	0	0
T2	50362	18290	0	0
T3	439148	204724	0	0
T4	2565	45	0	0
T5	52167	9394	0	0
T14	2387	32	0	0
T15	47181	16431	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	379601928	378801015	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	379601928	104530463	0	0
GntImpliesValid_A	379601928	104530463	0	0
GrantKnown_A	379601928	378801015	0	0
IdxKnown_A	379601928	378801015	0	0
IndexIsCorrect_A	379601928	104530463	0	0
NoReadyValidNoGrant_A	379601928	45933677	0	0
Priority_A	379601928	110353240	0	0
ReadyAndValidImplyGrant_A	379601928	104530463	0	0
ReqAndReadyImplyGrant_A	379601928	104530463	0	0
ReqImpliesValid_A	379601928	110353240	0	0
ValidKnown_A	379601928	378801015	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	104530463	0	0
T1	272325	116303	0	0
T2	50362	11516	0	0
T3	439148	170043	0	0
T4	2565	45	0	0
T5	52167	8967	0	0
T14	2387	32	0	0
T15	47181	13313	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	104530463	0	0
T1	272325	116303	0	0
T2	50362	11516	0	0
T3	439148	170043	0	0
T4	2565	45	0	0
T5	52167	8967	0	0
T14	2387	32	0	0
T15	47181	13313	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	104530463	0	0
T1	272325	116303	0	0
T2	50362	11516	0	0
T3	439148	170043	0	0
T4	2565	45	0	0
T5	52167	8967	0	0
T14	2387	32	0	0
T15	47181	13313	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	45933677	0	0
T1	272325	30940	0	0
T2	50362	15334	0	0
T3	439148	55075	0	0
T4	2565	148	0	0
T5	52167	26887	0	0
T14	2387	128	0	0
T15	47181	24391	0	0
T16	1282	128	0	0
T17	140627	2880	0	0
T18	116002	64	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	110353240	0	0
T1	272325	116303	0	0
T2	50362	18290	0	0
T3	439148	204724	0	0
T4	2565	45	0	0
T5	52167	9394	0	0
T14	2387	32	0	0
T15	47181	16431	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	104530463	0	0
T1	272325	116303	0	0
T2	50362	11516	0	0
T3	439148	170043	0	0
T4	2565	45	0	0
T5	52167	8967	0	0
T14	2387	32	0	0
T15	47181	13313	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	104530463	0	0
T1	272325	116303	0	0
T2	50362	11516	0	0
T3	439148	170043	0	0
T4	2565	45	0	0
T5	52167	8967	0	0
T14	2387	32	0	0
T15	47181	13313	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	110353240	0	0
T1	272325	116303	0	0
T2	50362	18290	0	0
T3	439148	204724	0	0
T4	2565	45	0	0
T5	52167	9394	0	0
T14	2387	32	0	0
T15	47181	16431	0	0
T16	1282	32	0	0
T17	140627	1828	0	0
T18	116002	292	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	379601928	378801015	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	379601928	100362490	0	0
GntImpliesValid_A	379601928	100362490	0	0
GrantKnown_A	379601928	378801015	0	0
IdxKnown_A	379601928	378801015	0	0
IndexIsCorrect_A	379601928	100362490	0	0
NoReadyValidNoGrant_A	379601928	43806793	0	0
Priority_A	379601928	106221225	0	0
ReadyAndValidImplyGrant_A	379601928	100362490	0	0
ReqAndReadyImplyGrant_A	379601928	100362490	0	0
ReqImpliesValid_A	379601928	106221225	0	0
ValidKnown_A	379601928	378801015	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	100362490	0	0
T2	50362	10581	0	0
T3	439148	125990	0	0
T4	2565	317	0	0
T5	52167	10279	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	8043	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	65004	0	0
T24	0	7926	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	100362490	0	0
T2	50362	10581	0	0
T3	439148	125990	0	0
T4	2565	317	0	0
T5	52167	10279	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	8043	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	65004	0	0
T24	0	7926	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	100362490	0	0
T2	50362	10581	0	0
T3	439148	125990	0	0
T4	2565	317	0	0
T5	52167	10279	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	8043	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	65004	0	0
T24	0	7926	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	43806793	0	0
T2	50362	12536	0	0
T3	439148	43229	0	0
T4	2565	11	0	0
T5	52167	28890	0	0
T14	2387	0	0	0
T15	47181	13691	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	41753	0	0
T22	0	16	0	0
T23	0	21	0	0
T24	0	283671	0	0
T25	0	22	0	0
T29	63246	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	106221225	0	0
T2	50362	18085	0	0
T3	439148	152181	0	0
T4	2565	317	0	0
T5	52167	10879	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	9753	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	76515	0	0
T24	0	125127	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	100362490	0	0
T2	50362	10581	0	0
T3	439148	125990	0	0
T4	2565	317	0	0
T5	52167	10279	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	8043	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	65004	0	0
T24	0	7926	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	100362490	0	0
T2	50362	10581	0	0
T3	439148	125990	0	0
T4	2565	317	0	0
T5	52167	10279	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	8043	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	65004	0	0
T24	0	7926	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	106221225	0	0
T2	50362	18085	0	0
T3	439148	152181	0	0
T4	2565	317	0	0
T5	52167	10879	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	9753	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	76515	0	0
T24	0	125127	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	379601928	378801015	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	379601928	100362407	0	0
GntImpliesValid_A	379601928	100362407	0	0
GrantKnown_A	379601928	378801015	0	0
IdxKnown_A	379601928	378801015	0	0
IndexIsCorrect_A	379601928	100362407	0	0
NoReadyValidNoGrant_A	379601928	43806794	0	0
Priority_A	379601928	106221141	0	0
ReadyAndValidImplyGrant_A	379601928	100362407	0	0
ReqAndReadyImplyGrant_A	379601928	100362407	0	0
ReqImpliesValid_A	379601928	106221141	0	0
ValidKnown_A	379601928	378801015	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	100362407	0	0
T2	50362	10581	0	0
T3	439148	125990	0	0
T4	2565	317	0	0
T5	52167	10279	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	8043	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	65004	0	0
T24	0	7926	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	100362407	0	0
T2	50362	10581	0	0
T3	439148	125990	0	0
T4	2565	317	0	0
T5	52167	10279	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	8043	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	65004	0	0
T24	0	7926	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	100362407	0	0
T2	50362	10581	0	0
T3	439148	125990	0	0
T4	2565	317	0	0
T5	52167	10279	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	8043	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	65004	0	0
T24	0	7926	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	43806794	0	0
T2	50362	12536	0	0
T3	439148	43229	0	0
T4	2565	11	0	0
T5	52167	28890	0	0
T14	2387	0	0	0
T15	47181	13691	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	41753	0	0
T22	0	16	0	0
T23	0	21	0	0
T24	0	283671	0	0
T25	0	22	0	0
T29	63246	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	106221141	0	0
T2	50362	18085	0	0
T3	439148	152181	0	0
T4	2565	317	0	0
T5	52167	10879	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	9753	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	76515	0	0
T24	0	125127	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	100362407	0	0
T2	50362	10581	0	0
T3	439148	125990	0	0
T4	2565	317	0	0
T5	52167	10279	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	8043	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	65004	0	0
T24	0	7926	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	100362407	0	0
T2	50362	10581	0	0
T3	439148	125990	0	0
T4	2565	317	0	0
T5	52167	10279	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	8043	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	65004	0	0
T24	0	7926	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	106221141	0	0
T2	50362	18085	0	0
T3	439148	152181	0	0
T4	2565	317	0	0
T5	52167	10879	0	0
T10	0	66	0	0
T14	2387	0	0	0
T15	47181	9753	0	0
T16	1282	0	0	0
T17	140627	0	0	0
T18	116002	0	0	0
T20	0	76515	0	0
T24	0	125127	0	0
T29	63246	0	0	0
T42	0	61338	0	0
T52	0	9425	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	379601928	378801015	0	0
T1	272325	259778	0	0
T2	50362	50266	0	0
T3	439148	439066	0	0
T4	2565	2478	0	0
T5	52167	52093	0	0
T14	2387	2303	0	0
T15	47181	47044	0	0
T16	1282	1220	0	0
T17	140627	140535	0	0
T18	116002	115931	0	0