Unified Coverage Report

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A	0	0	375460172	0	0	0
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A	0	0	375460172	0	0	0
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A	0	0	375460172	0	0	0
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A	0	0	375460172	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A	0	0	375460172	0	0	0
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A	0	0	375460172	0	0	0
tb.dut.FpvSecCmRdReqFifoRptrCheck_A	0	0	375460172	0	0	0
tb.dut.FpvSecCmRdReqFifoWptrCheck_A	0	0	375460172	0	0	0
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A	0	0	375460172	0	0	0
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A	0	0	375460172	0	0	0
tb.dut.PrimRspPayLoad_A	0	0	375460172	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	375460172	0	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	375460172	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A	0	0	375460172	0	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M	0	0	375460172	0	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	375460172	0	0	1036
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	375460172	0	0	1036
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	375460172	0	0	1036
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	375460172	0	0	1036
tb.dut.u_prog_tl_gate.OutStandingOvfl_A	0	0	375460172	0	0	0
tb.dut.u_tl_gate.OutStandingOvfl_A	0	0	375460172	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty	0	0	375460172	0	0	0
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull	0	0	375460172	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A	0	0	375460172	0	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375460172	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A	0	0	375460172	0	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	375460172	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FifoDepthCheck_A	0	0	1042	1042	0	0
tb.dut.FlashAddrKnown_A	0	0	375460172	264999979	0	0
tb.dut.FlashAddrKnown_AKnownEnable	0	0	375460172	374632290	0	0
tb.dut.FlashKnownO_A	0	0	375460172	374632290	0	0
tb.dut.FlashProgKnown_A	0	0	375460172	160805051	0	0
tb.dut.FlashProgKnown_AKnownEnable	0	0	375460172	374632290	0	0
tb.dut.FpvSecCmAddrCntAlertCheck_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmArbFsmCheck_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmLcCtrlFsmCheck_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmPageCntAlertCheck_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmProgCnt_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmRdCnt_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmRdRspFifoRptrCheck_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmRdRspFifoWptrCheck_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmSeedCntAlertCheck_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmTlLcGateFsm_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmTlProgLcGateFsm_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmWipeIdx_A	0	0	375460172	50	0	0
tb.dut.FpvSecCmWordCntAlertCheck_A	0	0	375460172	50	0	0
tb.dut.IntrErrO_A	0	0	375460172	374632290	0	0
tb.dut.IntrOpDoneKnownO_A	0	0	375460172	374632290	0	0
tb.dut.IntrProgEmptyKnownO_A	0	0	375460172	374632290	0	0
tb.dut.IntrProgLvlKnownO_A	0	0	375460172	374632290	0	0
tb.dut.IntrProgRdFullKnownO_A	0	0	375460172	374632290	0	0
tb.dut.IntrRdLvlKnownO_A	0	0	375460172	374632290	0	0
tb.dut.MemRspPayLoad_A	0	0	375460172	5384904	0	0
tb.dut.MemRspPayLoad_AKnownEnable	0	0	375460172	374632290	0	0
tb.dut.MemTlAReadyKnownO_A	0	0	375460172	374632290	0	0
tb.dut.MemTlDValidKnownO_A	0	0	375460172	374632290	0	0
tb.dut.PrimRspPayLoad_AKnownEnable	0	0	375460172	374632290	0	0
tb.dut.PrimTlAReadyKnownO_A	0	0	375460172	374632290	0	0
tb.dut.PrimTlDValidKnownO_A	0	0	375460172	374632290	0	0
tb.dut.RspPayLoad_A	0	0	375328760	37564786	0	0
tb.dut.RspPayLoad_AKnownEnable	0	0	375460172	374632290	0	0
tb.dut.TdoEnIsOne_A	0	0	375460172	374632290	0	0
tb.dut.TdoKnown_A	0	0	375460172	374632290	0	0
tb.dut.TlAReadyKnownO_A	0	0	375460172	374632290	0	0
tb.dut.TlDValidKnownO_A	0	0	375460172	374632290	0	0
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A	0	0	378378303	4372	0	0
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A	0	0	378378303	1882	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A	0	0	378378303	3119	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A	0	0	378378303	3253	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A	0	0	378378303	3451	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A	0	0	378378303	3898	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A	0	0	378378303	3735	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A	0	0	378378303	3934	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A	0	0	378378303	4223	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A	0	0	378378303	4044	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A	0	0	378378303	2883	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A	0	0	378378303	3666	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A	0	0	378378303	3029	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A	0	0	378378303	2444	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A	0	0	378378303	2325	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A	0	0	378378303	2978	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A	0	0	378378303	2437	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A	0	0	378378303	2080	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A	0	0	378378303	2976	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A	0	0	378378303	2018	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A	0	0	378378303	2407	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A	0	0	378378303	2538	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A	0	0	378378303	3958	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A	0	0	378378303	3175	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A	0	0	378378303	4047	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A	0	0	378378303	4269	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A	0	0	378378303	1949	0	0
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A	0	0	378378303	3136	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A	0	0	378378303	4231	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A	0	0	378378303	4097	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A	0	0	378378303	3545	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A	0	0	378378303	3676	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A	0	0	378378303	3424	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A	0	0	378378303	3461	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A	0	0	378378303	3831	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A	0	0	378378303	3505	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A	0	0	378378303	3782	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A	0	0	378378303	3609	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A	0	0	378378303	2051	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A	0	0	378378303	2442	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A	0	0	378378303	2398	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A	0	0	378378303	2487	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A	0	0	378378303	2892	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A	0	0	378378303	2849	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A	0	0	378378303	2096	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A	0	0	378378303	1998	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A	0	0	378378303	2804	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A	0	0	378378303	1469	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A	0	0	378378303	4068	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A	0	0	378378303	2504	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A	0	0	378378303	3562	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A	0	0	378378303	2595	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A	0	0	378378303	2474	0	0
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A	0	0	378378303	3048	0	0
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A	0	0	378378303	2984	0	0
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A	0	0	378378303	3724	0	0
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A	0	0	378378303	2517	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A	0	0	378378303	2702	0	0
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A	0	0	378378303	2846	0	0
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A	0	0	378378303	1698	0	0
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A	0	0	378378303	3747	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A	0	0	378378303	2721	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A	0	0	378378303	3130	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A	0	0	378378303	2094	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A	0	0	378378303	2787	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A	0	0	378378303	2691	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A	0	0	378378303	3072	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A	0	0	378378303	2251	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A	0	0	378378303	1666	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A	0	0	378378303	3918	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A	0	0	378378303	4046	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A	0	0	378378303	3279	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A	0	0	378378303	4292	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A	0	0	378378303	3507	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A	0	0	378378303	3994	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A	0	0	378378303	3705	0	0
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A	0	0	378378303	3369	0	0
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A	0	0	378378303	2188	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A	0	0	378378303	2094	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A	0	0	378378303	2455	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A	0	0	378378303	2009	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A	0	0	378378303	2319	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A	0	0	378378303	2003	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A	0	0	378378303	2392	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A	0	0	378378303	2557	0	0
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A	0	0	378378303	2518	0	0
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A	0	0	378378303	1547	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A	0	0	375460172	50	0	0
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A	0	0	375460172	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A	0	0	375460172	50	0	0
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A	0	0	375460172	50	0	0
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A	0	0	375460172	50	0	0
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	0	0	375460172	28	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	378378281	31707107	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	378378281	377467984	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	378378281	377467984	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	378378281	38416700	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	378378281	377467984	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	378378281	377467984	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	1252	1252	0	0

Go next page

	ASSERT	PROPERTIES	SEQUENCES
Total	1020	0	10
Category 0	1020	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	1020	0	10
Severity 0	1020	0	10

	NUMBER	PERCENT
Total Number	1020	100.00
Uncovered	27	2.65
Success	993	97.35
Failure	0	0.00
Incomplete	15	1.47
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	3	30.00
All Matches	7	70.00
First Matches	7	70.00