Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	280732	1		T1	1		T2	2		T3	2
all_values[1]	280732	1		T1	1		T2	2		T3	2
all_values[2]	280732	1		T1	1		T2	2		T3	2
all_values[3]	280732	1		T1	1		T2	2		T3	2
all_values[4]	280732	1		T1	1		T2	2		T3	2
all_values[5]	280732	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	567876	1		T1	6		T2	12		T3	12
auto[1]	1116516	1		T22	5636		T32	14136		T25	5712

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	826067	1		T1	4		T2	7		T3	6
auto[1]	858325	1		T1	2		T2	5		T3	6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	280590	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	142	1		T258	4		T259	1		T260	2
all_values[1]	auto[0]	auto[1]	280577	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	155	1		T258	2		T259	3		T260	3
all_values[2]	auto[0]	auto[0]	1621	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	60	1		T258	1		T259	1		T260	1
all_values[2]	auto[1]	auto[0]	278996	1		T22	1409		T32	3534		T25	1428
all_values[2]	auto[1]	auto[1]	55	1		T258	1		T260	2		T319	2
all_values[3]	auto[0]	auto[0]	1636	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	62	1		T258	1		T259	2		T260	1
all_values[3]	auto[1]	auto[0]	74412	1		T22	1409		T32	1767		T25	1428
all_values[3]	auto[1]	auto[1]	204622	1		T32	1767		T33	1635		T29	549
all_values[4]	auto[0]	auto[0]	1134	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	532	1		T2	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	187745	1		T22	1		T32	1767		T25	1
all_values[4]	auto[1]	auto[1]	91321	1		T22	1408		T32	1767		T25	1427
all_values[5]	auto[0]	auto[0]	1529	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	135	1		T3	1		T6	1		T34	1
all_values[5]	auto[1]	auto[0]	278994	1		T22	1409		T32	3534		T25	1428
all_values[5]	auto[1]	auto[1]	74	1		T258	2		T260	3		T321	4