Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	233755	1		T2	2		T3	812		T4	624
auto[FlashEraseBank]	262489	1		T3	500		T4	509		T5	8

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	246154	1		T3	1312		T4	1133		T5	13
auto[FlashOpProgram]	230854	1		T5	3		T6	1572		T16	15
auto[FlashOpErase]	15236	1		T2	2		T21	19		T27	11
auto[FlashOpInvalid]	4000	1		T17	200		T148	200		T211	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	246154	1		T3	1312		T4	1133		T5	13
op[FlashOpProgram]	230854	1		T5	3		T6	1572		T16	15
op[FlashOpErase]	15236	1		T2	2		T21	19		T27	11
read_erase_read	535	1		T21	17		T27	1		T36	1
read_prog_read	853	1		T5	3		T6	12		T39	8

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	357191	1		T2	2		T3	1133		T4	825
auto[FlashPartInfo]	135509	1		T3	169		T4	303		T5	12
auto[FlashPartInfo1]	868	1		T3	2		T4	2		T39	1
auto[FlashPartInfo2]	2676	1		T3	8		T4	3		T5	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	174695	1		T3	1133		T4	825		T5	3
auto[FlashPartData]	auto[FlashOpProgram]	174947	1		T6	1404		T39	489		T7	2
auto[FlashPartData]	auto[FlashOpErase]	3615	1		T2	2		T21	7		T17	99
auto[FlashPartData]	auto[FlashOpInvalid]	3934	1		T17	198		T148	196		T211	198
auto[FlashPartInfo]	auto[FlashOpRead]	69011	1		T3	169		T4	303		T5	9
auto[FlashPartInfo]	auto[FlashOpProgram]	54847	1		T5	3		T6	157		T16	15
auto[FlashPartInfo]	auto[FlashOpErase]	11595	1		T21	12		T27	11		T17	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	56	1		T17	2		T148	4		T211	2
auto[FlashPartInfo1]	auto[FlashOpRead]	697	1		T3	2		T4	2		T39	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T126	1		T154	1		T129	32
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T134	1		T409	2		T157	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T158	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1751	1		T3	8		T4	3		T5	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	896	1		T6	11		T22	7		T76	2
auto[FlashPartInfo2]	auto[FlashOpErase]	21	1		T67	1		T152	2		T126	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T161	2		T410	2		T411	2