Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30089	1		T17	400		T74	484		T42	764
auto[1]	34	1		T76	4		T24	1		T190	4
auto[2]	38	1		T210	2		T153	3		T347	2
auto[3]	370	1		T21	20		T35	1		T210	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7641	1		T21	5		T17	100		T74	121
evic_idx[1]	7639	1		T21	6		T17	100		T74	121
evic_idx[2]	7634	1		T21	5		T17	100		T74	121
evic_idx[3]	7617	1		T21	4		T17	100		T74	121

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29599	1		T21	20		T17	400		T74	484
evic_op[2]	340	1		T76	4		T24	1		T66	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[3]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7316	1		T17	100		T74	121		T42	191
evic_idx[0]	evic_op[1]	auto[1]	3	1		T153	1		T285	1		T348	1
evic_idx[0]	evic_op[1]	auto[2]	1	1		T153	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	80	1		T21	5		T151	7		T152	6
evic_idx[0]	evic_op[2]	auto[0]	66	1		T149	1		T57	4		T130	1
evic_idx[0]	evic_op[2]	auto[1]	5	1		T76	1		T24	1		T190	1
evic_idx[0]	evic_op[2]	auto[2]	3	1		T210	1		T349	1		T350	1
evic_idx[0]	evic_op[2]	auto[3]	19	1		T149	1		T209	1		T351	1
evic_idx[1]	evic_op[1]	auto[0]	7315	1		T17	100		T74	121		T42	191
evic_idx[1]	evic_op[1]	auto[1]	3	1		T153	2		T348	1		-	-
evic_idx[1]	evic_op[1]	auto[2]	2	1		T153	1		T163	1		-	-
evic_idx[1]	evic_op[1]	auto[3]	87	1		T21	6		T151	8		T152	5
evic_idx[1]	evic_op[2]	auto[0]	68	1		T66	1		T57	4		T130	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T76	1		T190	1		T352	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T353	1		T349	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	10	1		T282	1		T116	1		T354	1
evic_idx[2]	evic_op[1]	auto[0]	7316	1		T17	100		T74	121		T42	191
evic_idx[2]	evic_op[1]	auto[1]	4	1		T153	3		T348	1		-	-
evic_idx[2]	evic_op[1]	auto[2]	1	1		T347	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	82	1		T21	5		T151	7		T152	6
evic_idx[2]	evic_op[2]	auto[0]	62	1		T57	4		T130	1		T355	4
evic_idx[2]	evic_op[2]	auto[1]	6	1		T76	1		T190	1		T352	1
evic_idx[2]	evic_op[2]	auto[2]	3	1		T210	1		T349	1		T356	1
evic_idx[2]	evic_op[2]	auto[3]	12	1		T35	1		T210	1		T357	1
evic_idx[3]	evic_op[1]	auto[0]	7314	1		T17	100		T74	121		T42	191
evic_idx[3]	evic_op[1]	auto[1]	4	1		T153	3		T348	1		-	-
evic_idx[3]	evic_op[1]	auto[2]	2	1		T153	1		T347	1		-	-
evic_idx[3]	evic_op[1]	auto[3]	69	1		T21	4		T151	4		T152	4
evic_idx[3]	evic_op[2]	auto[0]	64	1		T358	1		T57	4		T130	1
evic_idx[3]	evic_op[2]	auto[1]	5	1		T76	1		T190	1		T352	1
evic_idx[3]	evic_op[2]	auto[3]	11	1		T279	1		T280	1		T359	1