Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	34436	1		T328	15347		T329	2635		T330	2484
rd_lvl[2]	27394	1		T328	11325		T329	1400		T330	1703
rd_lvl[3]	4855	1		T329	444		T330	937		T331	661
rd_lvl[4]	18566	1		T329	344		T332	869		T330	968
rd_lvl[5]	12354	1		T333	2314		T334	612		T335	2271
rd_lvl[6]	14378	1		T333	2375		T334	182		T336	2294
rd_lvl[7]	6697	1		T337	729		T336	768		T335	53
rd_lvl[8]	13026	1		T334	14		T337	415		T338	2097
rd_lvl[9]	5350	1		T32	626		T339	528		T337	20
rd_lvl[10]	6129	1		T32	1141		T33	184		T339	962
rd_lvl[11]	3702	1		T33	1451		T340	326		T334	12
rd_lvl[12]	6078	1		T340	244		T144	1291		T341	445
rd_lvl[13]	3419	1		T30	70		T144	492		T341	1088
rd_lvl[14]	9079	1		T30	16		T31	177		T342	1341
rd_lvl[15]	3899	1		T29	355		T342	329		T343	178