Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	280732	1		T1	1		T2	2		T3	2
all_pins[1]	280732	1		T1	1		T2	2		T3	2
all_pins[2]	280732	1		T1	1		T2	2		T3	2
all_pins[3]	280732	1		T1	1		T2	2		T3	2
all_pins[4]	280732	1		T1	1		T2	2		T3	2
all_pins[5]	280732	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1415062	1		T1	6		T2	12		T3	12
values[0x1]	269330	1		T22	1408		T32	3534		T25	1427
transitions[0x0=>0x1]	245845	1		T22	1408		T32	3534		T25	1427
transitions[0x1=>0x0]	245833	1		T22	1408		T32	3534		T25	1427

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280590	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	142	1		T258	4		T259	1		T260	2
all_pins[0]	transitions[0x0=>0x1]	79	1		T258	3		T260	2		T321	5
all_pins[0]	transitions[0x1=>0x0]	92	1		T258	1		T259	2		T260	3
all_pins[1]	values[0x0]	280577	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	155	1		T258	2		T259	3		T260	3
all_pins[1]	transitions[0x0=>0x1]	123	1		T258	1		T259	3		T260	2
all_pins[1]	transitions[0x1=>0x0]	1455	1		T29	194		T343	4		T360	198
all_pins[2]	values[0x0]	279245	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	1487	1		T29	194		T343	4		T360	198
all_pins[2]	transitions[0x0=>0x1]	47	1		T258	1		T260	2		T319	2
all_pins[2]	transitions[0x1=>0x0]	169596	1		T32	1767		T33	1635		T29	355
all_pins[3]	values[0x0]	109696	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	171036	1		T32	1767		T33	1635		T29	549
all_pins[3]	transitions[0x0=>0x1]	149156	1		T32	1767		T33	1635		T29	355
all_pins[3]	transitions[0x1=>0x0]	74556	1		T22	1408		T32	1767		T25	1427
all_pins[4]	values[0x0]	184296	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	96436	1		T22	1408		T32	1767		T25	1427
all_pins[4]	transitions[0x0=>0x1]	96411	1		T22	1408		T32	1767		T25	1427
all_pins[4]	transitions[0x1=>0x0]	49	1		T258	2		T260	3		T321	3
all_pins[5]	values[0x0]	280658	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	74	1		T258	2		T260	3		T321	4
all_pins[5]	transitions[0x0=>0x1]	29	1		T258	1		T260	1		T326	2
all_pins[5]	transitions[0x1=>0x0]	85	1		T258	2		T259	1		T321	1