Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1		T258	4		T259	4		T260	4
all_values[1]	266	1		T258	4		T259	4		T260	4
all_values[2]	266	1		T258	4		T259	4		T260	4
all_values[3]	266	1		T258	4		T259	4		T260	4
all_values[4]	266	1		T258	4		T259	4		T260	4
all_values[5]	266	1		T258	4		T259	4		T260	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	854	1		T258	11		T259	11		T260	8
auto[1]	742	1		T258	13		T259	13		T260	16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	497	1		T258	10		T259	12		T260	8
auto[1]	1099	1		T258	14		T259	12		T260	16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	925	1		T258	18		T259	18		T260	14
auto[1]	671	1		T258	6		T259	6		T260	10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	80	1		T258	2		T259	1		T260	2
all_values[0]	auto[0]	auto[1]	auto[1]	68	1		T258	1		T259	1		T260	1
all_values[0]	auto[1]	auto[0]	auto[1]	71	1		T259	1		T319	1		T320	1
all_values[0]	auto[1]	auto[1]	auto[1]	47	1		T258	1		T259	1		T260	1
all_values[1]	auto[0]	auto[0]	auto[1]	85	1		T258	1		T259	1		T321	4
all_values[1]	auto[0]	auto[1]	auto[1]	77	1		T258	3		T259	3		T260	2
all_values[1]	auto[1]	auto[0]	auto[1]	59	1		T260	2		T320	3		T322	1
all_values[1]	auto[1]	auto[1]	auto[1]	45	1		T320	2		T322	1		T323	1
all_values[2]	auto[0]	auto[0]	auto[0]	75	1		T258	2		T259	2		T320	3
all_values[2]	auto[0]	auto[1]	auto[0]	76	1		T259	1		T260	1		T321	4
all_values[2]	auto[1]	auto[0]	auto[1]	66	1		T258	1		T320	1		T322	2
all_values[2]	auto[1]	auto[1]	auto[1]	49	1		T258	1		T259	1		T260	3
all_values[3]	auto[0]	auto[0]	auto[0]	86	1		T258	2		T259	2		T260	1
all_values[3]	auto[0]	auto[1]	auto[0]	73	1		T260	2		T321	3		T320	2
all_values[3]	auto[1]	auto[0]	auto[1]	65	1		T259	1		T260	1		T319	2
all_values[3]	auto[1]	auto[1]	auto[1]	42	1		T258	2		T259	1		T320	1
all_values[4]	auto[0]	auto[0]	auto[0]	48	1		T258	3		T259	3		T260	2
all_values[4]	auto[0]	auto[0]	auto[1]	29	1		T322	2		T324	1		T325	1
all_values[4]	auto[0]	auto[1]	auto[0]	40	1		T258	1		T259	1		T260	1
all_values[4]	auto[0]	auto[1]	auto[1]	34	1		T321	1		T319	2		T320	1
all_values[4]	auto[1]	auto[0]	auto[1]	63	1		T320	4		T322	1		T324	2
all_values[4]	auto[1]	auto[1]	auto[1]	52	1		T260	1		T321	1		T319	2
all_values[5]	auto[0]	auto[0]	auto[0]	54	1		T322	2		T324	3		T326	1
all_values[5]	auto[0]	auto[0]	auto[1]	23	1		T320	1		T324	2		T327	1
all_values[5]	auto[0]	auto[1]	auto[0]	45	1		T258	2		T259	3		T260	1
all_values[5]	auto[0]	auto[1]	auto[1]	32	1		T258	1		T260	1		T321	3
all_values[5]	auto[1]	auto[0]	auto[1]	50	1		T320	2		T322	2		T323	1
all_values[5]	auto[1]	auto[1]	auto[1]	62	1		T258	1		T259	1		T260	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal