| T1083 |
/workspace/coverage/default/9.flash_ctrl_ro_derr.3284771674 |
|
|
Jun 26 07:17:46 PM PDT 24 |
Jun 26 07:20:48 PM PDT 24 |
1108986600 ps |
| T374 |
/workspace/coverage/default/44.flash_ctrl_disable.4289077870 |
|
|
Jun 26 07:24:16 PM PDT 24 |
Jun 26 07:24:45 PM PDT 24 |
19173100 ps |
| T1084 |
/workspace/coverage/default/5.flash_ctrl_re_evict.2687825630 |
|
|
Jun 26 07:15:49 PM PDT 24 |
Jun 26 07:16:29 PM PDT 24 |
138509700 ps |
| T1085 |
/workspace/coverage/default/4.flash_ctrl_phy_arb.697002492 |
|
|
Jun 26 07:14:58 PM PDT 24 |
Jun 26 07:20:31 PM PDT 24 |
86208100 ps |
| T1086 |
/workspace/coverage/default/47.flash_ctrl_disable.4142711580 |
|
|
Jun 26 07:24:31 PM PDT 24 |
Jun 26 07:24:55 PM PDT 24 |
14556000 ps |
| T1087 |
/workspace/coverage/default/2.flash_ctrl_ro_serr.408948946 |
|
|
Jun 26 07:13:25 PM PDT 24 |
Jun 26 07:15:35 PM PDT 24 |
3902699600 ps |
| T1088 |
/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.2980072076 |
|
|
Jun 26 07:23:27 PM PDT 24 |
Jun 26 07:24:50 PM PDT 24 |
2644947800 ps |
| T1089 |
/workspace/coverage/default/3.flash_ctrl_ro_derr.2163724573 |
|
|
Jun 26 07:14:30 PM PDT 24 |
Jun 26 07:17:05 PM PDT 24 |
645742400 ps |
| T1090 |
/workspace/coverage/default/75.flash_ctrl_connect.3816671032 |
|
|
Jun 26 07:25:10 PM PDT 24 |
Jun 26 07:25:29 PM PDT 24 |
52339800 ps |
| T1091 |
/workspace/coverage/default/15.flash_ctrl_prog_reset.1172029802 |
|
|
Jun 26 07:19:43 PM PDT 24 |
Jun 26 07:23:15 PM PDT 24 |
9604974800 ps |
| T1092 |
/workspace/coverage/default/6.flash_ctrl_wo.2634078629 |
|
|
Jun 26 07:16:00 PM PDT 24 |
Jun 26 07:18:46 PM PDT 24 |
7546862400 ps |
| T1093 |
/workspace/coverage/default/16.flash_ctrl_sec_info_access.1663958644 |
|
|
Jun 26 07:20:08 PM PDT 24 |
Jun 26 07:21:12 PM PDT 24 |
6278709100 ps |
| T1094 |
/workspace/coverage/default/15.flash_ctrl_intr_rd.1949808174 |
|
|
Jun 26 07:19:44 PM PDT 24 |
Jun 26 07:22:34 PM PDT 24 |
14397530600 ps |
| T1095 |
/workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1840725743 |
|
|
Jun 26 07:23:48 PM PDT 24 |
Jun 26 07:26:26 PM PDT 24 |
11368947400 ps |
| T113 |
/workspace/coverage/default/2.flash_ctrl_sec_cm.1049137848 |
|
|
Jun 26 07:13:35 PM PDT 24 |
Jun 26 08:36:15 PM PDT 24 |
2305860000 ps |
| T1096 |
/workspace/coverage/default/2.flash_ctrl_invalid_op.3522455926 |
|
|
Jun 26 07:13:26 PM PDT 24 |
Jun 26 07:14:53 PM PDT 24 |
4022757000 ps |
| T1097 |
/workspace/coverage/default/2.flash_ctrl_alert_test.3124265166 |
|
|
Jun 26 07:14:01 PM PDT 24 |
Jun 26 07:14:16 PM PDT 24 |
81330500 ps |
| T1098 |
/workspace/coverage/default/4.flash_ctrl_lcmgr_intg.1330067378 |
|
|
Jun 26 07:15:38 PM PDT 24 |
Jun 26 07:15:54 PM PDT 24 |
63783000 ps |
| T1099 |
/workspace/coverage/default/16.flash_ctrl_smoke.3314005010 |
|
|
Jun 26 07:19:53 PM PDT 24 |
Jun 26 07:21:57 PM PDT 24 |
92677100 ps |
| T1100 |
/workspace/coverage/default/4.flash_ctrl_disable.2349568558 |
|
|
Jun 26 07:15:21 PM PDT 24 |
Jun 26 07:15:45 PM PDT 24 |
55324800 ps |
| T1101 |
/workspace/coverage/default/18.flash_ctrl_invalid_op.2925946723 |
|
|
Jun 26 07:20:45 PM PDT 24 |
Jun 26 07:22:09 PM PDT 24 |
8659837800 ps |
| T1102 |
/workspace/coverage/default/13.flash_ctrl_connect.4104110154 |
|
|
Jun 26 07:19:05 PM PDT 24 |
Jun 26 07:19:22 PM PDT 24 |
44162900 ps |
| T1103 |
/workspace/coverage/default/78.flash_ctrl_connect.233469432 |
|
|
Jun 26 07:25:10 PM PDT 24 |
Jun 26 07:25:29 PM PDT 24 |
43706300 ps |
| T1104 |
/workspace/coverage/default/1.flash_ctrl_derr_detect.2342578618 |
|
|
Jun 26 07:12:48 PM PDT 24 |
Jun 26 07:14:40 PM PDT 24 |
127039500 ps |
| T1105 |
/workspace/coverage/default/24.flash_ctrl_smoke.85659517 |
|
|
Jun 26 07:21:54 PM PDT 24 |
Jun 26 07:24:46 PM PDT 24 |
85870500 ps |
| T1106 |
/workspace/coverage/default/48.flash_ctrl_smoke.4167049577 |
|
|
Jun 26 07:24:31 PM PDT 24 |
Jun 26 07:26:37 PM PDT 24 |
178663600 ps |
| T1107 |
/workspace/coverage/default/2.flash_ctrl_host_dir_rd.2347642590 |
|
|
Jun 26 07:13:11 PM PDT 24 |
Jun 26 07:14:27 PM PDT 24 |
47906000 ps |
| T1108 |
/workspace/coverage/default/39.flash_ctrl_sec_info_access.3813019855 |
|
|
Jun 26 07:23:51 PM PDT 24 |
Jun 26 07:25:02 PM PDT 24 |
3123826700 ps |
| T1109 |
/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2973456617 |
|
|
Jun 26 07:19:31 PM PDT 24 |
Jun 26 07:19:48 PM PDT 24 |
15275100 ps |
| T1110 |
/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1870812173 |
|
|
Jun 26 07:17:46 PM PDT 24 |
Jun 26 07:18:05 PM PDT 24 |
15773700 ps |
| T1111 |
/workspace/coverage/default/28.flash_ctrl_intr_rd.1006125352 |
|
|
Jun 26 07:22:22 PM PDT 24 |
Jun 26 07:25:00 PM PDT 24 |
4086970100 ps |
| T1112 |
/workspace/coverage/default/67.flash_ctrl_connect.3319748692 |
|
|
Jun 26 07:24:56 PM PDT 24 |
Jun 26 07:25:15 PM PDT 24 |
25430200 ps |
| T1113 |
/workspace/coverage/default/26.flash_ctrl_smoke.3210743580 |
|
|
Jun 26 07:22:08 PM PDT 24 |
Jun 26 07:25:00 PM PDT 24 |
68549100 ps |
| T1114 |
/workspace/coverage/default/31.flash_ctrl_intr_rd.66689960 |
|
|
Jun 26 07:23:10 PM PDT 24 |
Jun 26 07:25:46 PM PDT 24 |
1318067400 ps |
| T1115 |
/workspace/coverage/default/16.flash_ctrl_connect.3224668958 |
|
|
Jun 26 07:20:08 PM PDT 24 |
Jun 26 07:20:24 PM PDT 24 |
49228900 ps |
| T192 |
/workspace/coverage/default/4.flash_ctrl_mid_op_rst.3282806154 |
|
|
Jun 26 07:14:59 PM PDT 24 |
Jun 26 07:16:15 PM PDT 24 |
670407200 ps |
| T1116 |
/workspace/coverage/default/4.flash_ctrl_oversize_error.3185769360 |
|
|
Jun 26 07:15:10 PM PDT 24 |
Jun 26 07:19:05 PM PDT 24 |
6422706400 ps |
| T1117 |
/workspace/coverage/default/29.flash_ctrl_smoke.346431117 |
|
|
Jun 26 07:22:40 PM PDT 24 |
Jun 26 07:24:48 PM PDT 24 |
51272100 ps |
| T1118 |
/workspace/coverage/default/7.flash_ctrl_disable.3040906292 |
|
|
Jun 26 07:16:42 PM PDT 24 |
Jun 26 07:17:07 PM PDT 24 |
30914900 ps |
| T1119 |
/workspace/coverage/default/17.flash_ctrl_rw_evict.3616200248 |
|
|
Jun 26 07:20:31 PM PDT 24 |
Jun 26 07:21:06 PM PDT 24 |
232657200 ps |
| T1120 |
/workspace/coverage/default/30.flash_ctrl_disable.3045131380 |
|
|
Jun 26 07:23:09 PM PDT 24 |
Jun 26 07:23:33 PM PDT 24 |
27859700 ps |
| T1121 |
/workspace/coverage/default/12.flash_ctrl_otp_reset.1341830409 |
|
|
Jun 26 07:18:36 PM PDT 24 |
Jun 26 07:20:35 PM PDT 24 |
271411500 ps |
| T1122 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2603901391 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:49 PM PDT 24 |
51319900 ps |
| T258 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1203213519 |
|
|
Jun 26 07:05:10 PM PDT 24 |
Jun 26 07:05:26 PM PDT 24 |
17590100 ps |
| T95 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3661251660 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:08 PM PDT 24 |
218968000 ps |
| T58 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2898275730 |
|
|
Jun 26 07:04:27 PM PDT 24 |
Jun 26 07:05:49 PM PDT 24 |
5218773200 ps |
| T59 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3402644374 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:04:41 PM PDT 24 |
122181000 ps |
| T99 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.4121024281 |
|
|
Jun 26 07:04:21 PM PDT 24 |
Jun 26 07:04:41 PM PDT 24 |
186973300 ps |
| T60 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1816288406 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:54 PM PDT 24 |
18735000 ps |
| T259 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3749726145 |
|
|
Jun 26 07:05:09 PM PDT 24 |
Jun 26 07:05:24 PM PDT 24 |
16046700 ps |
| T96 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.224999401 |
|
|
Jun 26 07:04:32 PM PDT 24 |
Jun 26 07:04:53 PM PDT 24 |
254118500 ps |
| T260 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.4014086447 |
|
|
Jun 26 07:04:57 PM PDT 24 |
Jun 26 07:05:13 PM PDT 24 |
36812700 ps |
| T97 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1706334011 |
|
|
Jun 26 07:04:50 PM PDT 24 |
Jun 26 07:17:26 PM PDT 24 |
720616300 ps |
| T321 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1168853830 |
|
|
Jun 26 07:05:04 PM PDT 24 |
Jun 26 07:05:19 PM PDT 24 |
18940800 ps |
| T98 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2980488046 |
|
|
Jun 26 07:04:43 PM PDT 24 |
Jun 26 07:05:02 PM PDT 24 |
47180400 ps |
| T228 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3895233398 |
|
|
Jun 26 07:04:27 PM PDT 24 |
Jun 26 07:12:14 PM PDT 24 |
1635881700 ps |
| T319 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1269321681 |
|
|
Jun 26 07:05:08 PM PDT 24 |
Jun 26 07:05:24 PM PDT 24 |
16155500 ps |
| T244 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3650355151 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:03 PM PDT 24 |
48794500 ps |
| T320 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2759348014 |
|
|
Jun 26 07:04:45 PM PDT 24 |
Jun 26 07:05:02 PM PDT 24 |
55149500 ps |
| T245 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3448488319 |
|
|
Jun 26 07:05:00 PM PDT 24 |
Jun 26 07:05:23 PM PDT 24 |
726638600 ps |
| T229 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1913139289 |
|
|
Jun 26 07:04:32 PM PDT 24 |
Jun 26 07:04:53 PM PDT 24 |
173713400 ps |
| T1123 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3910492138 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:04 PM PDT 24 |
19990200 ps |
| T1124 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3439063099 |
|
|
Jun 26 07:04:50 PM PDT 24 |
Jun 26 07:05:05 PM PDT 24 |
23044100 ps |
| T1125 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1010336365 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:05:13 PM PDT 24 |
52724100 ps |
| T322 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.4144578007 |
|
|
Jun 26 07:06:18 PM PDT 24 |
Jun 26 07:06:35 PM PDT 24 |
16340900 ps |
| T230 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1410416022 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:04:44 PM PDT 24 |
43692000 ps |
| T324 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3313179539 |
|
|
Jun 26 07:05:07 PM PDT 24 |
Jun 26 07:05:22 PM PDT 24 |
15537900 ps |
| T326 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.429851247 |
|
|
Jun 26 07:05:08 PM PDT 24 |
Jun 26 07:05:23 PM PDT 24 |
44250100 ps |
| T1126 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2878002663 |
|
|
Jun 26 07:04:25 PM PDT 24 |
Jun 26 07:04:41 PM PDT 24 |
31603900 ps |
| T246 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.849299160 |
|
|
Jun 26 07:04:44 PM PDT 24 |
Jun 26 07:05:03 PM PDT 24 |
136853800 ps |
| T247 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3105107106 |
|
|
Jun 26 07:04:47 PM PDT 24 |
Jun 26 07:05:06 PM PDT 24 |
35683500 ps |
| T325 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2119786998 |
|
|
Jun 26 07:04:56 PM PDT 24 |
Jun 26 07:05:12 PM PDT 24 |
82336000 ps |
| T297 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.196060402 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:05:23 PM PDT 24 |
3092843800 ps |
| T1127 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3665610262 |
|
|
Jun 26 07:04:57 PM PDT 24 |
Jun 26 07:05:16 PM PDT 24 |
11881100 ps |
| T323 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3027930870 |
|
|
Jun 26 07:04:56 PM PDT 24 |
Jun 26 07:05:12 PM PDT 24 |
15750800 ps |
| T1128 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2954928819 |
|
|
Jun 26 07:05:08 PM PDT 24 |
Jun 26 07:05:24 PM PDT 24 |
25552400 ps |
| T1129 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2802523041 |
|
|
Jun 26 07:05:02 PM PDT 24 |
Jun 26 07:05:16 PM PDT 24 |
24804100 ps |
| T327 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.4093917756 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:03 PM PDT 24 |
15513200 ps |
| T248 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2671915574 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:55 PM PDT 24 |
52306600 ps |
| T233 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2642554288 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:12:11 PM PDT 24 |
182338500 ps |
| T249 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1549308297 |
|
|
Jun 26 07:04:47 PM PDT 24 |
Jun 26 07:05:08 PM PDT 24 |
412687500 ps |
| T1130 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3841813837 |
|
|
Jun 26 07:04:58 PM PDT 24 |
Jun 26 07:05:16 PM PDT 24 |
49948400 ps |
| T1131 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2624804515 |
|
|
Jun 26 07:04:21 PM PDT 24 |
Jun 26 07:04:37 PM PDT 24 |
21165100 ps |
| T1132 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.4290006359 |
|
|
Jun 26 07:05:09 PM PDT 24 |
Jun 26 07:05:24 PM PDT 24 |
59993500 ps |
| T1133 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2108865249 |
|
|
Jun 26 07:04:56 PM PDT 24 |
Jun 26 07:05:12 PM PDT 24 |
58665400 ps |
| T1134 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2247314366 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:04:41 PM PDT 24 |
15860700 ps |
| T1135 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.4174509741 |
|
|
Jun 26 07:05:07 PM PDT 24 |
Jun 26 07:05:21 PM PDT 24 |
116253400 ps |
| T1136 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2979532326 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:04:42 PM PDT 24 |
71921300 ps |
| T1137 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3445130137 |
|
|
Jun 26 07:05:07 PM PDT 24 |
Jun 26 07:05:22 PM PDT 24 |
24745300 ps |
| T231 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1857278633 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:54 PM PDT 24 |
74906500 ps |
| T232 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2487462119 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:50 PM PDT 24 |
35013200 ps |
| T234 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3566525018 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:04:44 PM PDT 24 |
48936400 ps |
| T1138 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.65150443 |
|
|
Jun 26 07:04:21 PM PDT 24 |
Jun 26 07:04:39 PM PDT 24 |
44467400 ps |
| T298 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3101821399 |
|
|
Jun 26 07:04:57 PM PDT 24 |
Jun 26 07:05:16 PM PDT 24 |
41404000 ps |
| T235 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.442250983 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:07 PM PDT 24 |
86156600 ps |
| T1139 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.7494527 |
|
|
Jun 26 07:04:11 PM PDT 24 |
Jun 26 07:04:29 PM PDT 24 |
161637000 ps |
| T1140 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3811095528 |
|
|
Jun 26 07:04:56 PM PDT 24 |
Jun 26 07:05:12 PM PDT 24 |
26123100 ps |
| T1141 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3651822863 |
|
|
Jun 26 07:04:12 PM PDT 24 |
Jun 26 07:04:48 PM PDT 24 |
229155400 ps |
| T299 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3443296630 |
|
|
Jun 26 07:04:48 PM PDT 24 |
Jun 26 07:05:10 PM PDT 24 |
104413600 ps |
| T272 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.547439634 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:56 PM PDT 24 |
190935700 ps |
| T1142 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1589486940 |
|
|
Jun 26 07:05:04 PM PDT 24 |
Jun 26 07:05:18 PM PDT 24 |
81356000 ps |
| T271 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1549624829 |
|
|
Jun 26 07:04:32 PM PDT 24 |
Jun 26 07:04:52 PM PDT 24 |
40958900 ps |
| T1143 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2904939610 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:24 PM PDT 24 |
173814900 ps |
| T1144 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.355752002 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:04 PM PDT 24 |
35727600 ps |
| T1145 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2506316655 |
|
|
Jun 26 07:04:48 PM PDT 24 |
Jun 26 07:05:03 PM PDT 24 |
99633100 ps |
| T361 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4128181585 |
|
|
Jun 26 07:04:50 PM PDT 24 |
Jun 26 07:05:10 PM PDT 24 |
102319500 ps |
| T1146 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1248582727 |
|
|
Jun 26 07:04:58 PM PDT 24 |
Jun 26 07:05:18 PM PDT 24 |
328778200 ps |
| T1147 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.724080870 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:05:00 PM PDT 24 |
454758100 ps |
| T1148 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.4034667510 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:04:40 PM PDT 24 |
15821000 ps |
| T1149 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1021285231 |
|
|
Jun 26 07:04:45 PM PDT 24 |
Jun 26 07:05:05 PM PDT 24 |
22215900 ps |
| T1150 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.485519122 |
|
|
Jun 26 07:05:08 PM PDT 24 |
Jun 26 07:05:23 PM PDT 24 |
18468000 ps |
| T237 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.4246162314 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:04:39 PM PDT 24 |
31254600 ps |
| T1151 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2708101784 |
|
|
Jun 26 07:04:11 PM PDT 24 |
Jun 26 07:04:30 PM PDT 24 |
30590400 ps |
| T300 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3855177292 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:06:49 PM PDT 24 |
58439520700 ps |
| T1152 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3515311651 |
|
|
Jun 26 07:05:12 PM PDT 24 |
Jun 26 07:05:26 PM PDT 24 |
92488000 ps |
| T1153 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.414708697 |
|
|
Jun 26 07:04:32 PM PDT 24 |
Jun 26 07:04:48 PM PDT 24 |
15511600 ps |
| T1154 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1856179332 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:01 PM PDT 24 |
24582000 ps |
| T1155 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2763412447 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:05:19 PM PDT 24 |
7834105700 ps |
| T270 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1640727967 |
|
|
Jun 26 07:06:27 PM PDT 24 |
Jun 26 07:14:01 PM PDT 24 |
1326176800 ps |
| T1156 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.535593973 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:05:04 PM PDT 24 |
552781000 ps |
| T1157 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1436760268 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:50 PM PDT 24 |
17518500 ps |
| T1158 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.535346449 |
|
|
Jun 26 07:04:31 PM PDT 24 |
Jun 26 07:04:49 PM PDT 24 |
199012700 ps |
| T277 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2607622551 |
|
|
Jun 26 07:04:43 PM PDT 24 |
Jun 26 07:12:27 PM PDT 24 |
354451300 ps |
| T1159 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2897864406 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:50 PM PDT 24 |
21004400 ps |
| T1160 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1637223637 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:04:40 PM PDT 24 |
44118100 ps |
| T301 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3349272219 |
|
|
Jun 26 07:04:48 PM PDT 24 |
Jun 26 07:05:07 PM PDT 24 |
289575500 ps |
| T1161 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1817390005 |
|
|
Jun 26 07:04:26 PM PDT 24 |
Jun 26 07:04:42 PM PDT 24 |
55158500 ps |
| T1162 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3068503722 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:53 PM PDT 24 |
38649700 ps |
| T1163 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2216795281 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:04:56 PM PDT 24 |
132069600 ps |
| T1164 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3600070073 |
|
|
Jun 26 07:06:27 PM PDT 24 |
Jun 26 07:06:42 PM PDT 24 |
15161800 ps |
| T1165 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3501793984 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:54 PM PDT 24 |
43267300 ps |
| T1166 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1528006551 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:04:55 PM PDT 24 |
923462900 ps |
| T1167 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.4234034836 |
|
|
Jun 26 07:05:10 PM PDT 24 |
Jun 26 07:05:25 PM PDT 24 |
48148400 ps |
| T1168 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.759553500 |
|
|
Jun 26 07:04:35 PM PDT 24 |
Jun 26 07:04:53 PM PDT 24 |
18597000 ps |
| T275 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3000610299 |
|
|
Jun 26 07:04:48 PM PDT 24 |
Jun 26 07:19:55 PM PDT 24 |
678129800 ps |
| T1169 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.656482300 |
|
|
Jun 26 07:04:32 PM PDT 24 |
Jun 26 07:05:19 PM PDT 24 |
91546000 ps |
| T1170 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.282252334 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:04:41 PM PDT 24 |
60093700 ps |
| T1171 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3003163331 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:52 PM PDT 24 |
85535200 ps |
| T1172 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1875087492 |
|
|
Jun 26 07:04:59 PM PDT 24 |
Jun 26 07:05:19 PM PDT 24 |
29440800 ps |
| T238 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1982111498 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:04:39 PM PDT 24 |
16730600 ps |
| T1173 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.524489419 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:55 PM PDT 24 |
19413100 ps |
| T1174 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2751615458 |
|
|
Jun 26 07:04:57 PM PDT 24 |
Jun 26 07:05:16 PM PDT 24 |
47601400 ps |
| T1175 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3144645820 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:04:42 PM PDT 24 |
119134200 ps |
| T1176 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2099594332 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:55 PM PDT 24 |
556794100 ps |
| T1177 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.746391531 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:52 PM PDT 24 |
160898300 ps |
| T1178 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3103584704 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:04:38 PM PDT 24 |
149264900 ps |
| T274 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3247000638 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:56 PM PDT 24 |
52374000 ps |
| T1179 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1690440736 |
|
|
Jun 26 07:04:35 PM PDT 24 |
Jun 26 07:04:52 PM PDT 24 |
18311800 ps |
| T257 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4077161064 |
|
|
Jun 26 07:04:32 PM PDT 24 |
Jun 26 07:20:05 PM PDT 24 |
836775800 ps |
| T239 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2925551735 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:04:40 PM PDT 24 |
152545600 ps |
| T1180 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2941904401 |
|
|
Jun 26 07:04:43 PM PDT 24 |
Jun 26 07:04:59 PM PDT 24 |
15845400 ps |
| T1181 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.447826005 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:58 PM PDT 24 |
90364000 ps |
| T1182 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1251919133 |
|
|
Jun 26 07:04:32 PM PDT 24 |
Jun 26 07:04:52 PM PDT 24 |
53811300 ps |
| T1183 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2255963122 |
|
|
Jun 26 07:04:57 PM PDT 24 |
Jun 26 07:05:19 PM PDT 24 |
329753800 ps |
| T1184 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3701750519 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:51 PM PDT 24 |
14798500 ps |
| T1185 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2197980604 |
|
|
Jun 26 07:05:08 PM PDT 24 |
Jun 26 07:05:23 PM PDT 24 |
45189100 ps |
| T1186 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2187549290 |
|
|
Jun 26 07:04:12 PM PDT 24 |
Jun 26 07:04:32 PM PDT 24 |
49973800 ps |
| T363 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.549702462 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:10:54 PM PDT 24 |
1769405500 ps |
| T1187 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.347895618 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:01 PM PDT 24 |
37430500 ps |
| T267 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1276806758 |
|
|
Jun 26 07:05:00 PM PDT 24 |
Jun 26 07:20:07 PM PDT 24 |
3580012400 ps |
| T1188 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1179514901 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:53 PM PDT 24 |
32158500 ps |
| T1189 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2592210707 |
|
|
Jun 26 07:04:32 PM PDT 24 |
Jun 26 07:04:47 PM PDT 24 |
15194900 ps |
| T1190 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3423237632 |
|
|
Jun 26 07:04:45 PM PDT 24 |
Jun 26 07:05:04 PM PDT 24 |
427464500 ps |
| T1191 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3306006973 |
|
|
Jun 26 07:04:48 PM PDT 24 |
Jun 26 07:05:06 PM PDT 24 |
141081300 ps |
| T1192 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.548966427 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:04:41 PM PDT 24 |
121933000 ps |
| T1193 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2982002523 |
|
|
Jun 26 07:04:56 PM PDT 24 |
Jun 26 07:05:12 PM PDT 24 |
49604800 ps |
| T1194 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1369423909 |
|
|
Jun 26 07:04:48 PM PDT 24 |
Jun 26 07:05:06 PM PDT 24 |
16827900 ps |
| T1195 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3249108644 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:51 PM PDT 24 |
47823200 ps |
| T1196 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.458972593 |
|
|
Jun 26 07:04:09 PM PDT 24 |
Jun 26 07:04:24 PM PDT 24 |
11655800 ps |
| T264 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3918256436 |
|
|
Jun 26 07:04:57 PM PDT 24 |
Jun 26 07:05:18 PM PDT 24 |
57215600 ps |
| T252 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1912388397 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:08 PM PDT 24 |
59528100 ps |
| T253 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2864556582 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:04 PM PDT 24 |
113890500 ps |
| T1197 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3133641762 |
|
|
Jun 26 07:04:21 PM PDT 24 |
Jun 26 07:04:38 PM PDT 24 |
108674800 ps |
| T261 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3057106429 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:04 PM PDT 24 |
113092000 ps |
| T1198 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2723494223 |
|
|
Jun 26 07:06:27 PM PDT 24 |
Jun 26 07:06:44 PM PDT 24 |
26074900 ps |
| T1199 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2579596056 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:04:41 PM PDT 24 |
167683500 ps |
| T1200 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3291816291 |
|
|
Jun 26 07:04:43 PM PDT 24 |
Jun 26 07:04:58 PM PDT 24 |
16932200 ps |
| T255 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3967251240 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:04:43 PM PDT 24 |
85017900 ps |
| T302 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1702603139 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:12:15 PM PDT 24 |
439788100 ps |
| T1201 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3840283799 |
|
|
Jun 26 07:04:56 PM PDT 24 |
Jun 26 07:05:16 PM PDT 24 |
194861800 ps |
| T303 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.82115633 |
|
|
Jun 26 07:04:21 PM PDT 24 |
Jun 26 07:05:31 PM PDT 24 |
1786723000 ps |
| T1202 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3293346285 |
|
|
Jun 26 07:04:44 PM PDT 24 |
Jun 26 07:05:02 PM PDT 24 |
36014800 ps |
| T1203 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1745550909 |
|
|
Jun 26 07:04:35 PM PDT 24 |
Jun 26 07:04:52 PM PDT 24 |
98643100 ps |
| T1204 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3071209643 |
|
|
Jun 26 07:04:57 PM PDT 24 |
Jun 26 07:05:16 PM PDT 24 |
497672000 ps |
| T256 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.837943442 |
|
|
Jun 26 07:04:50 PM PDT 24 |
Jun 26 07:11:15 PM PDT 24 |
195421000 ps |
| T1205 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.120886836 |
|
|
Jun 26 07:04:47 PM PDT 24 |
Jun 26 07:05:05 PM PDT 24 |
26691100 ps |
| T1206 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2875784054 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:02 PM PDT 24 |
25951400 ps |
| T262 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1661238712 |
|
|
Jun 26 07:04:44 PM PDT 24 |
Jun 26 07:17:18 PM PDT 24 |
671611900 ps |
| T1207 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3799427898 |
|
|
Jun 26 07:04:12 PM PDT 24 |
Jun 26 07:04:29 PM PDT 24 |
17519600 ps |
| T1208 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.286802936 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:52 PM PDT 24 |
12316100 ps |
| T263 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3735906334 |
|
|
Jun 26 07:04:14 PM PDT 24 |
Jun 26 07:17:16 PM PDT 24 |
938197300 ps |
| T1209 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3686209150 |
|
|
Jun 26 07:05:10 PM PDT 24 |
Jun 26 07:05:25 PM PDT 24 |
50859800 ps |
| T1210 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.437821571 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:10:57 PM PDT 24 |
382056700 ps |
| T1211 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2727122020 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:03 PM PDT 24 |
39321700 ps |
| T1212 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.2740017169 |
|
|
Jun 26 07:04:28 PM PDT 24 |
Jun 26 07:04:43 PM PDT 24 |
16167900 ps |
| T1213 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.1365049236 |
|
|
Jun 26 07:04:57 PM PDT 24 |
Jun 26 07:05:14 PM PDT 24 |
83149300 ps |
| T304 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.284988250 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:05:14 PM PDT 24 |
98136800 ps |
| T254 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3658742386 |
|
|
Jun 26 07:04:47 PM PDT 24 |
Jun 26 07:05:07 PM PDT 24 |
122217300 ps |
| T1214 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1505392083 |
|
|
Jun 26 07:04:32 PM PDT 24 |
Jun 26 07:04:49 PM PDT 24 |
17628300 ps |
| T1215 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3523845373 |
|
|
Jun 26 07:04:57 PM PDT 24 |
Jun 26 07:05:19 PM PDT 24 |
157957500 ps |
| T268 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3594178207 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:11:55 PM PDT 24 |
681301100 ps |
| T1216 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.370582022 |
|
|
Jun 26 07:04:45 PM PDT 24 |
Jun 26 07:05:01 PM PDT 24 |
31200100 ps |
| T265 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2132827771 |
|
|
Jun 26 07:04:12 PM PDT 24 |
Jun 26 07:04:36 PM PDT 24 |
108167800 ps |
| T1217 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.426845020 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:04:42 PM PDT 24 |
14492000 ps |
| T305 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2568504949 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:05:37 PM PDT 24 |
12969896300 ps |
| T1218 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2973706880 |
|
|
Jun 26 07:05:11 PM PDT 24 |
Jun 26 07:05:26 PM PDT 24 |
32823200 ps |
| T1219 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.684524316 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:04:42 PM PDT 24 |
11694800 ps |
| T306 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1404637855 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:54 PM PDT 24 |
751815500 ps |
| T266 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.714243810 |
|
|
Jun 26 07:04:58 PM PDT 24 |
Jun 26 07:17:43 PM PDT 24 |
1378553300 ps |
| T1220 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.557017858 |
|
|
Jun 26 07:04:44 PM PDT 24 |
Jun 26 07:05:02 PM PDT 24 |
30494400 ps |
| T1221 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2876487439 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:04:47 PM PDT 24 |
111066700 ps |
| T273 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1545674051 |
|
|
Jun 26 07:04:25 PM PDT 24 |
Jun 26 07:04:48 PM PDT 24 |
238992800 ps |
| T1222 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.150590422 |
|
|
Jun 26 07:05:08 PM PDT 24 |
Jun 26 07:05:23 PM PDT 24 |
99289800 ps |
| T1223 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.383073792 |
|
|
Jun 26 07:05:09 PM PDT 24 |
Jun 26 07:05:24 PM PDT 24 |
26815800 ps |
| T1224 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1811157092 |
|
|
Jun 26 07:04:46 PM PDT 24 |
Jun 26 07:05:05 PM PDT 24 |
77858400 ps |
| T1225 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2616912136 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:04:51 PM PDT 24 |
19089600 ps |
| T1226 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.179095138 |
|
|
Jun 26 07:04:36 PM PDT 24 |
Jun 26 07:04:57 PM PDT 24 |
38151400 ps |
| T240 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1578074999 |
|
|
Jun 26 07:04:21 PM PDT 24 |
Jun 26 07:04:37 PM PDT 24 |
17658900 ps |
| T1227 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2747598510 |
|
|
Jun 26 07:05:04 PM PDT 24 |
Jun 26 07:05:18 PM PDT 24 |
247786600 ps |
| T1228 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1663610436 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:50 PM PDT 24 |
133521500 ps |
| T1229 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1397925592 |
|
|
Jun 26 07:04:35 PM PDT 24 |
Jun 26 07:04:55 PM PDT 24 |
19676900 ps |
| T1230 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3247353339 |
|
|
Jun 26 07:04:45 PM PDT 24 |
Jun 26 07:05:00 PM PDT 24 |
24516000 ps |
| T1231 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1503756499 |
|
|
Jun 26 07:05:09 PM PDT 24 |
Jun 26 07:05:25 PM PDT 24 |
82281100 ps |
| T1232 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2436620714 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:50 PM PDT 24 |
11992000 ps |
| T1233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2071278890 |
|
|
Jun 26 07:04:21 PM PDT 24 |
Jun 26 07:04:36 PM PDT 24 |
93933000 ps |
| T276 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2915824457 |
|
|
Jun 26 07:04:35 PM PDT 24 |
Jun 26 07:04:59 PM PDT 24 |
209373500 ps |
| T1234 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3481573574 |
|
|
Jun 26 07:04:42 PM PDT 24 |
Jun 26 07:19:54 PM PDT 24 |
2683772600 ps |
| T307 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1377214156 |
|
|
Jun 26 07:04:48 PM PDT 24 |
Jun 26 07:05:11 PM PDT 24 |
213471100 ps |
| T1235 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1059032920 |
|
|
Jun 26 07:04:59 PM PDT 24 |
Jun 26 07:05:17 PM PDT 24 |
17159600 ps |
| T308 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2415160825 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:04:56 PM PDT 24 |
913280200 ps |
| T1236 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2023432999 |
|
|
Jun 26 07:05:02 PM PDT 24 |
Jun 26 07:05:20 PM PDT 24 |
107679900 ps |
| T364 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1748543682 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:19:51 PM PDT 24 |
2508802000 ps |
| T1237 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1910784972 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:52 PM PDT 24 |
133757500 ps |
| T1238 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.4274293967 |
|
|
Jun 26 07:04:38 PM PDT 24 |
Jun 26 07:04:54 PM PDT 24 |
96676800 ps |
| T1239 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1952343639 |
|
|
Jun 26 07:04:23 PM PDT 24 |
Jun 26 07:04:42 PM PDT 24 |
105467000 ps |
| T1240 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.845701422 |
|
|
Jun 26 07:05:03 PM PDT 24 |
Jun 26 07:05:18 PM PDT 24 |
14568300 ps |
| T1241 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3846787773 |
|
|
Jun 26 07:04:25 PM PDT 24 |
Jun 26 07:04:47 PM PDT 24 |
106226500 ps |
| T1242 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1694581099 |
|
|
Jun 26 07:04:33 PM PDT 24 |
Jun 26 07:04:52 PM PDT 24 |
197367800 ps |
| T1243 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2662182514 |
|
|
Jun 26 07:04:45 PM PDT 24 |
Jun 26 07:05:08 PM PDT 24 |
607984700 ps |
| T1244 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2340456681 |
|
|
Jun 26 07:04:57 PM PDT 24 |
Jun 26 07:05:13 PM PDT 24 |
26030700 ps |
| T1245 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.299637567 |
|
|
Jun 26 07:04:24 PM PDT 24 |
Jun 26 07:04:47 PM PDT 24 |
81797200 ps |
| T1246 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.737027561 |
|
|
Jun 26 07:04:56 PM PDT 24 |
Jun 26 07:05:17 PM PDT 24 |
317416000 ps |
| T1247 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.4267593604 |
|
|
Jun 26 07:04:48 PM PDT 24 |
Jun 26 07:05:07 PM PDT 24 |
219190500 ps |
| T241 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2581554308 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:04:39 PM PDT 24 |
16462200 ps |
| T278 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.602966116 |
|
|
Jun 26 07:04:34 PM PDT 24 |
Jun 26 07:11:03 PM PDT 24 |
978153000 ps |
| T1248 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3132004275 |
|
|
Jun 26 07:04:36 PM PDT 24 |
Jun 26 07:04:57 PM PDT 24 |
940628800 ps |
| T1249 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2938779628 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:04:42 PM PDT 24 |
14417500 ps |
| T1250 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1581702220 |
|
|
Jun 26 07:04:58 PM PDT 24 |
Jun 26 07:05:16 PM PDT 24 |
60469100 ps |
| T1251 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.955616704 |
|
|
Jun 26 07:04:22 PM PDT 24 |
Jun 26 07:04:55 PM PDT 24 |
29406200 ps |
| T1252 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1880716935 |
|
|
Jun 26 07:04:45 PM PDT 24 |
Jun 26 07:05:04 PM PDT 24 |
97009900 ps |