Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 27351476 1 T1 4819 T2 65 T3 64
full_word 7643137 1 T1 13064 T2 43 T3 43


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 34994333 1 T1 17883 T2 108 T3 107
auto[TlIntgErrCmd] 83 1 T70 4 T224 2 T289 3
auto[TlIntgErrData] 93 1 T70 3 T224 2 T204 2
auto[TlIntgErrBoth] 104 1 T70 3 T224 6 T204 8


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30680770 1 T1 4264 T2 59 T3 60
auto[1] 4313843 1 T1 13619 T2 49 T3 47


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 26676513 1 T1 2157 T2 59 T3 58
auto[TlIntgErrNone] partial auto[1] 674701 1 T1 2662 T2 6 T3 6
auto[TlIntgErrNone] full_word auto[0] 4004127 1 T1 2107 T3 2 T12 126
auto[TlIntgErrNone] full_word auto[1] 3638992 1 T1 10957 T2 43 T3 41
auto[TlIntgErrCmd] partial auto[0] 36 1 T70 2 T224 1 T289 2
auto[TlIntgErrCmd] partial auto[1] 39 1 T70 1 T289 1 T291 2
auto[TlIntgErrCmd] full_word auto[0] 5 1 T70 1 T373 1 T374 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T224 1 T242 1 T376 1
auto[TlIntgErrData] partial auto[0] 46 1 T70 1 T224 1 T204 1
auto[TlIntgErrData] partial auto[1] 43 1 T70 2 T224 1 T204 1
auto[TlIntgErrData] full_word auto[0] 2 1 T376 1 T377 1 - -
auto[TlIntgErrData] full_word auto[1] 2 1 T248 1 T243 1 - -
auto[TlIntgErrBoth] partial auto[0] 40 1 T70 1 T224 4 T204 2
auto[TlIntgErrBoth] partial auto[1] 58 1 T70 1 T224 2 T204 6
auto[TlIntgErrBoth] full_word auto[0] 1 1 T289 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 5 1 T70 1 T289 1 T373 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 19206 1 T100 881 T70 9 T71 32
full_word 3775155 1 T20 10 T24 30 T23 6


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3794104 1 T20 10 T24 30 T23 6
auto[TlIntgErrCmd] 82 1 T70 3 T224 3 T204 2
auto[TlIntgErrData] 97 1 T70 4 T224 3 T204 4
auto[TlIntgErrBoth] 78 1 T70 2 T224 3 T204 4


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3770071 1 T20 10 T24 30 T23 6
auto[1] 24290 1 T100 1211 T70 5 T71 41


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1269 1 T100 40 T101 5 T201 10
auto[TlIntgErrNone] partial auto[1] 17697 1 T100 841 T71 32 T101 61
auto[TlIntgErrNone] full_word auto[0] 3768692 1 T20 10 T24 30 T23 6
auto[TlIntgErrNone] full_word auto[1] 6446 1 T100 370 T71 9 T101 23
auto[TlIntgErrCmd] partial auto[0] 26 1 T70 1 T291 3 T255 1
auto[TlIntgErrCmd] partial auto[1] 46 1 T70 2 T224 2 T204 2
auto[TlIntgErrCmd] full_word auto[0] 5 1 T224 1 T291 1 T255 1
auto[TlIntgErrCmd] full_word auto[1] 5 1 T289 1 T291 1 T255 1
auto[TlIntgErrData] partial auto[0] 50 1 T70 2 T224 2 T289 1
auto[TlIntgErrData] partial auto[1] 43 1 T70 2 T224 1 T204 4
auto[TlIntgErrData] full_word auto[0] 2 1 T255 1 T375 1 - -
auto[TlIntgErrData] full_word auto[1] 2 1 T376 1 T377 1 - -
auto[TlIntgErrBoth] partial auto[0] 25 1 T70 1 T204 2 T291 4
auto[TlIntgErrBoth] partial auto[1] 50 1 T70 1 T224 3 T204 2
auto[TlIntgErrBoth] full_word auto[0] 2 1 T378 2 - - - -
auto[TlIntgErrBoth] full_word auto[1] 1 1 T375 1 - - - -

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