Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T24,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T24,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T24,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T23,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T24,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T24,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T23,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T24,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T24,T23

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1530122724	1526700252	0	0
CheckNGreaterZero_A	4128	4128	0	0
GntImpliesReady_A	1530122724	406250142	0	0
GntImpliesValid_A	1530122724	406250142	0	0
GrantKnown_A	1530122724	1526700252	0	0
IdxKnown_A	1530122724	1526700252	0	0
IndexIsCorrect_A	1530122724	406250142	0	0
NoReadyValidNoGrant_A	1530122724	173372881	0	0
Priority_A	1530122724	429889887	0	0
ReadyAndValidImplyGrant_A	1530122724	406250142	0	0
ReqAndReadyImplyGrant_A	1530122724	406250142	0	0
ReqImpliesValid_A	1530122724	429889887	0	0
ValidKnown_A	1530122724	1526700252	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	1526700252	0	0
T1	740440	740408	0	0
T2	7960	7444	0	0
T3	5632	4692	0	0
T4	784052	783800	0	0
T5	9580	9372	0	0
T12	1601872	1601804	0	0
T13	17028	14076	0	0
T14	4328	3332	0	0
T20	11652	10996	0	0
T21	886216	833008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4128	4128	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T12	4	4	0	0
T13	4	4	0	0
T14	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	406250142	0	0
T1	740440	1586972	0	0
T2	7960	132	0	0
T3	5632	130	0	0
T4	784052	1608	0	0
T5	9580	350	0	0
T6	0	45374	0	0
T7	0	19908	0	0
T12	1601872	514600	0	0
T13	17028	408	0	0
T14	4328	134	0	0
T20	11652	442	0	0
T21	886216	274416	0	0
T23	0	162	0	0
T24	0	140162	0	0
T40	0	910	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	406250142	0	0
T1	740440	1586972	0	0
T2	7960	132	0	0
T3	5632	130	0	0
T4	784052	1608	0	0
T5	9580	350	0	0
T6	0	45374	0	0
T7	0	19908	0	0
T12	1601872	514600	0	0
T13	17028	408	0	0
T14	4328	134	0	0
T20	11652	442	0	0
T21	886216	274416	0	0
T23	0	162	0	0
T24	0	140162	0	0
T40	0	910	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	1526700252	0	0
T1	740440	740408	0	0
T2	7960	7444	0	0
T3	5632	4692	0	0
T4	784052	783800	0	0
T5	9580	9372	0	0
T12	1601872	1601804	0	0
T13	17028	14076	0	0
T14	4328	3332	0	0
T20	11652	10996	0	0
T21	886216	833008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	1526700252	0	0
T1	740440	740408	0	0
T2	7960	7444	0	0
T3	5632	4692	0	0
T4	784052	783800	0	0
T5	9580	9372	0	0
T12	1601872	1601804	0	0
T13	17028	14076	0	0
T14	4328	3332	0	0
T20	11652	10996	0	0
T21	886216	833008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	406250142	0	0
T1	740440	1586972	0	0
T2	7960	132	0	0
T3	5632	130	0	0
T4	784052	1608	0	0
T5	9580	350	0	0
T6	0	45374	0	0
T7	0	19908	0	0
T12	1601872	514600	0	0
T13	17028	408	0	0
T14	4328	134	0	0
T20	11652	442	0	0
T21	886216	274416	0	0
T23	0	162	0	0
T24	0	140162	0	0
T40	0	910	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	173372881	0	0
T1	370220	3392	0	0
T2	3980	512	0	0
T3	2816	520	0	0
T4	784052	1664	0	0
T5	9580	378	0	0
T6	0	123440	0	0
T7	0	26068	0	0
T8	0	603188	0	0
T12	1601872	2109952	0	0
T13	17028	1628	0	0
T14	4328	536	0	0
T20	11652	1000	0	0
T21	886216	65856	0	0
T23	4110	84	0	0
T24	191678	260	0	0
T28	0	254	0	0
T40	0	64	0	0
T58	2450	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	429889887	0	0
T1	740440	1586972	0	0
T2	7960	132	0	0
T3	5632	130	0	0
T4	784052	1608	0	0
T5	9580	350	0	0
T6	0	47076	0	0
T7	0	31440	0	0
T12	1601872	514600	0	0
T13	17028	408	0	0
T14	4328	134	0	0
T20	11652	442	0	0
T21	886216	274416	0	0
T23	0	162	0	0
T24	0	140162	0	0
T40	0	910	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	406250142	0	0
T1	740440	1586972	0	0
T2	7960	132	0	0
T3	5632	130	0	0
T4	784052	1608	0	0
T5	9580	350	0	0
T6	0	45374	0	0
T7	0	19908	0	0
T12	1601872	514600	0	0
T13	17028	408	0	0
T14	4328	134	0	0
T20	11652	442	0	0
T21	886216	274416	0	0
T23	0	162	0	0
T24	0	140162	0	0
T40	0	910	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	406250142	0	0
T1	740440	1586972	0	0
T2	7960	132	0	0
T3	5632	130	0	0
T4	784052	1608	0	0
T5	9580	350	0	0
T6	0	45374	0	0
T7	0	19908	0	0
T12	1601872	514600	0	0
T13	17028	408	0	0
T14	4328	134	0	0
T20	11652	442	0	0
T21	886216	274416	0	0
T23	0	162	0	0
T24	0	140162	0	0
T40	0	910	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	429889887	0	0
T1	740440	1586972	0	0
T2	7960	132	0	0
T3	5632	130	0	0
T4	784052	1608	0	0
T5	9580	350	0	0
T6	0	47076	0	0
T7	0	31440	0	0
T12	1601872	514600	0	0
T13	17028	408	0	0
T14	4328	134	0	0
T20	11652	442	0	0
T21	886216	274416	0	0
T23	0	162	0	0
T24	0	140162	0	0
T40	0	910	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	1526700252	0	0
T1	740440	740408	0	0
T2	7960	7444	0	0
T3	5632	4692	0	0
T4	784052	783800	0	0
T5	9580	9372	0	0
T12	1601872	1601804	0	0
T13	17028	14076	0	0
T14	4328	3332	0	0
T20	11652	10996	0	0
T21	886216	833008	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T24,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T24,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T24,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T23,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T24,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T24,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T23,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T24,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T24,T23

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382530681	381675063	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	382530681	107019155	0	0
GntImpliesValid_A	382530681	107019155	0	0
GrantKnown_A	382530681	381675063	0	0
IdxKnown_A	382530681	381675063	0	0
IndexIsCorrect_A	382530681	107019155	0	0
NoReadyValidNoGrant_A	382530681	44895197	0	0
Priority_A	382530681	112998670	0	0
ReadyAndValidImplyGrant_A	382530681	107019155	0	0
ReqAndReadyImplyGrant_A	382530681	107019155	0	0
ReqImpliesValid_A	382530681	112998670	0	0
ValidKnown_A	382530681	381675063	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	107019155	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	107019155	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	107019155	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	44895197	0	0
T1	185110	1696	0	0
T2	1990	256	0	0
T3	1408	260	0	0
T4	196013	832	0	0
T5	2395	175	0	0
T12	400468	530688	0	0
T13	4257	814	0	0
T14	1082	268	0	0
T20	2913	480	0	0
T21	221554	32928	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	112998670	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	107019155	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	107019155	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	112998670	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T24,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T24,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T24,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T23,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T24,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T24,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T23,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T24,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T24,T23

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382530681	381675063	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	382530681	107019167	0	0
GntImpliesValid_A	382530681	107019167	0	0
GrantKnown_A	382530681	381675063	0	0
IdxKnown_A	382530681	381675063	0	0
IndexIsCorrect_A	382530681	107019167	0	0
NoReadyValidNoGrant_A	382530681	44895142	0	0
Priority_A	382530681	112998737	0	0
ReadyAndValidImplyGrant_A	382530681	107019167	0	0
ReqAndReadyImplyGrant_A	382530681	107019167	0	0
ReqImpliesValid_A	382530681	112998737	0	0
ValidKnown_A	382530681	381675063	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	107019167	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	107019167	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	107019167	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	44895142	0	0
T1	185110	1696	0	0
T2	1990	256	0	0
T3	1408	260	0	0
T4	196013	832	0	0
T5	2395	175	0	0
T12	400468	530688	0	0
T13	4257	814	0	0
T14	1082	268	0	0
T20	2913	480	0	0
T21	221554	32928	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	112998737	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	107019167	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	107019167	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	112998737	0	0
T1	185110	114528	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	804	0	0
T5	2395	62	0	0
T12	400468	129403	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	216	0	0
T21	221554	137208	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T12
1	0	Covered	T20,T23,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T23,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T23,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T23,T6
1	0	Covered	T1,T2,T12
1	1	Covered	T20,T23,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T23,T6
1	1	Covered	T1,T2,T12

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T23,T6
1	1	Covered	T1,T2,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T23,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T23,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382530681	381675063	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	382530681	96105910	0	0
GntImpliesValid_A	382530681	96105910	0	0
GrantKnown_A	382530681	381675063	0	0
IdxKnown_A	382530681	381675063	0	0
IndexIsCorrect_A	382530681	96105910	0	0
NoReadyValidNoGrant_A	382530681	41791271	0	0
Priority_A	382530681	101946240	0	0
ReadyAndValidImplyGrant_A	382530681	96105910	0	0
ReqAndReadyImplyGrant_A	382530681	96105910	0	0
ReqImpliesValid_A	382530681	101946240	0	0
ValidKnown_A	382530681	381675063	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	96105910	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	22687	0	0
T7	0	9954	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	96105910	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	22687	0	0
T7	0	9954	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	96105910	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	22687	0	0
T7	0	9954	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	41791271	0	0
T4	196013	0	0	0
T5	2395	14	0	0
T6	0	61720	0	0
T7	0	13034	0	0
T8	0	301594	0	0
T12	400468	524288	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	20	0	0
T21	221554	0	0	0
T23	2055	42	0	0
T24	95839	130	0	0
T28	0	127	0	0
T40	0	32	0	0
T58	1225	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	101946240	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	23538	0	0
T7	0	15720	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	96105910	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	22687	0	0
T7	0	9954	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	96105910	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	22687	0	0
T7	0	9954	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	101946240	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	23538	0	0
T7	0	15720	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T12
1	0	Covered	T20,T23,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T23,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T23,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T23,T6
1	0	Covered	T1,T2,T12
1	1	Covered	T20,T23,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T23,T6
1	1	Covered	T1,T2,T12

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T23,T6
1	1	Covered	T1,T2,T12

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T23,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T23,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382530681	381675063	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	382530681	96105910	0	0
GntImpliesValid_A	382530681	96105910	0	0
GrantKnown_A	382530681	381675063	0	0
IdxKnown_A	382530681	381675063	0	0
IndexIsCorrect_A	382530681	96105910	0	0
NoReadyValidNoGrant_A	382530681	41791271	0	0
Priority_A	382530681	101946240	0	0
ReadyAndValidImplyGrant_A	382530681	96105910	0	0
ReqAndReadyImplyGrant_A	382530681	96105910	0	0
ReqImpliesValid_A	382530681	101946240	0	0
ValidKnown_A	382530681	381675063	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	96105910	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	22687	0	0
T7	0	9954	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	96105910	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	22687	0	0
T7	0	9954	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	96105910	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	22687	0	0
T7	0	9954	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	41791271	0	0
T4	196013	0	0	0
T5	2395	14	0	0
T6	0	61720	0	0
T7	0	13034	0	0
T8	0	301594	0	0
T12	400468	524288	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	20	0	0
T21	221554	0	0	0
T23	2055	42	0	0
T24	95839	130	0	0
T28	0	127	0	0
T40	0	32	0	0
T58	1225	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	101946240	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	23538	0	0
T7	0	15720	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	96105910	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	22687	0	0
T7	0	9954	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	96105910	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	22687	0	0
T7	0	9954	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	101946240	0	0
T1	185110	678958	0	0
T2	1990	2	0	0
T3	1408	0	0	0
T4	196013	0	0	0
T5	2395	113	0	0
T6	0	23538	0	0
T7	0	15720	0	0
T12	400468	127897	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	5	0	0
T21	221554	0	0	0
T23	0	81	0	0
T24	0	70081	0	0
T40	0	455	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0