Unified Coverage Report :: Module :: prim_arbiter_tree

Module : prim_arbiter_tree

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	96.15	97.15			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random	94.17	92.31	97.69			100.00	86.67
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random	94.17	92.31	97.69			100.00	86.67
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb	95.99	100.00	90.20			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb	96.97	100.00	94.12			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb	97.86	100.00	97.67			100.00	93.75
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb	97.86	100.00	97.67			100.00	93.75

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.76	100.00	91.03			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	92.31	97.69			100.00	86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.48	100.00	89.93			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.99	100.00	90.20			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.99	100.00	90.20			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_op

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	94.12			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	94.12			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_op

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_calc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.86	100.00	97.67			100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_prim_arbiter_tree_calc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Line Coverage for Module self-instances :

SCORE	LINE
94.17	92.31

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	LINE
94.17	92.31

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :

SCORE	LINE
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	LINE
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORE	LINE
95.99	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	LINE
96.97	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
97.86	97.67

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	COND
97.86	97.67

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T6,T7,T55
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable	T205
1	0	1	Unreachable	T6,T7,T55
1	1	0	Covered	T12,T20,T23
1	1	1	Unreachable	T12,T20,T23

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T23
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T12,T20,T23
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T55
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T20,T23

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
95.99	90.20

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	COND
96.97	94.12

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	49	96.08
Logical	51	49	96.08
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T115
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T115
1	0	1	Covered	T115
1	1	0	Covered	T12,T20,T23
1	1	1	Covered	T12,T20,T23

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T12,T20,T23
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T115,T116
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T115
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T20,T23

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Cond Coverage for Module self-instances :

SCORE	COND
94.17	97.69

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	COND
94.17	97.69

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T23,T6
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T23
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T23
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T25,T51,T189
1	1	Covered	T4,T20,T5

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T20,T5
1	1	0	Covered	T4,T20,T5
1	1	1	Covered	T4,T20,T5

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T20,T5
1	1	0	Covered	T4,T20,T5
1	1	1	Covered	T4,T20,T5

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T20,T5
1	1	0	Covered	T4,T20,T5
1	1	1	Covered	T4,T20,T5

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T20,T5
1	1	0	Covered	T4,T20,T5
1	1	1	Covered	T4,T20,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T25
1	0	Covered	T6,T25,T51

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T25,T51
1	0	Covered	T4,T20,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T28
1	0	Covered	T4,T20,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T20,T5
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T23,T6,T7
1	0	Covered	T4,T20,T5
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=4,DW=2,EnDataPort=0,IdxW=2,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
94.17	100.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

SCORE	BRANCH
94.17	100.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T20,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T20,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T20,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T20,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=16,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 + N=2,DW=129,EnDataPort=1,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	BRANCH
97.86	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

SCORE	BRANCH
95.99	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

SCORE	BRANCH
96.97	100.00

tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	6192	6192	0	0
GntImpliesReady_A	2147483647	69539019	0	0
GntImpliesValid_A	2147483647	69539019	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	69539019	0	0
LockArbDecision_A	2147483647	64734936	0	0
NoReadyValidNoGrant_A	2147483647	1955981816	0	0
ReadyAndValidImplyGrant_A	2147483647	69539019	0	0
ReqAndReadyImplyGrant_A	2147483647	69539019	0	0
ReqImpliesValid_A	2147483647	324571319	0	0
ReqStaysHighUntilGranted0_M	2147483647	64734216	0	0
RoundRobin_A	2147483647	20740	0	6162
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	1530122724	64735104	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1110660	1110612	0	0
T2	11940	11166	0	0
T3	8448	7038	0	0
T4	1176078	1175700	0	0
T5	14370	14058	0	0
T12	2402808	2402706	0	0
T13	25542	21114	0	0
T14	6492	4998	0	0
T20	17478	16494	0	0
T21	1329324	1249512	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6192	6192	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T12	6	6	0	0
T13	6	6	0	0
T14	6	6	0	0
T20	6	6	0	0
T21	6	6	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69539019	0	0
T1	740440	128	0	0
T2	7960	256	0	0
T3	5632	260	0	0
T4	980065	252	0	0
T5	14370	142	0	0
T6	337262	31082	0	0
T7	50945	19366	0	0
T8	0	8244	0	0
T12	1601872	1582336	0	0
T13	21285	814	0	0
T14	5410	268	0	0
T20	17478	506	0	0
T21	1329324	35708	0	0
T23	4110	56	0	0
T24	191678	2485	0	0
T28	6154	68	0	0
T40	2862	21	0	0
T41	0	52	0	0
T58	2450	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69539019	0	0
T1	740440	128	0	0
T2	7960	256	0	0
T3	5632	260	0	0
T4	980065	252	0	0
T5	14370	142	0	0
T6	337262	31082	0	0
T7	50945	19366	0	0
T8	0	8244	0	0
T12	1601872	1582336	0	0
T13	21285	814	0	0
T14	5410	268	0	0
T20	17478	506	0	0
T21	1329324	35708	0	0
T23	4110	56	0	0
T24	191678	2485	0	0
T28	6154	68	0	0
T40	2862	21	0	0
T41	0	52	0	0
T58	2450	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1110660	1110612	0	0
T2	11940	11166	0	0
T3	8448	7038	0	0
T4	1176078	1175700	0	0
T5	14370	14058	0	0
T12	2402808	2402706	0	0
T13	25542	21114	0	0
T14	6492	4998	0	0
T20	17478	16494	0	0
T21	1329324	1249512	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1110660	1110612	0	0
T2	11940	11166	0	0
T3	8448	7038	0	0
T4	1176078	1175700	0	0
T5	14370	14058	0	0
T12	2402808	2402706	0	0
T13	25542	21114	0	0
T14	6492	4998	0	0
T20	17478	16494	0	0
T21	1329324	1249512	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69539019	0	0
T1	740440	128	0	0
T2	7960	256	0	0
T3	5632	260	0	0
T4	980065	252	0	0
T5	14370	142	0	0
T6	337262	31082	0	0
T7	50945	19366	0	0
T8	0	8244	0	0
T12	1601872	1582336	0	0
T13	21285	814	0	0
T14	5410	268	0	0
T20	17478	506	0	0
T21	1329324	35708	0	0
T23	4110	56	0	0
T24	191678	2485	0	0
T28	6154	68	0	0
T40	2862	21	0	0
T41	0	52	0	0
T58	2450	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	64734936	0	0
T1	740440	128	0	0
T2	7960	256	0	0
T3	5632	260	0	0
T4	784052	0	0	0
T5	9580	128	0	0
T12	1601872	1582336	0	0
T13	17028	814	0	0
T14	4328	268	0	0
T20	11652	464	0	0
T21	886216	34960	0	0
T24	0	2432	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1955981816	0	0
T1	1110660	1110585	0	0
T2	11940	10590	0	0
T3	8448	6453	0	0
T4	1176078	1024033	0	0
T5	14370	10540	0	0
T12	2402808	2059868	0	0
T13	25542	19282	0	0
T14	6492	4395	0	0
T20	17478	13643	0	0
T21	1329324	1122249	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69539019	0	0
T1	740440	128	0	0
T2	7960	256	0	0
T3	5632	260	0	0
T4	980065	252	0	0
T5	14370	142	0	0
T6	337262	31082	0	0
T7	50945	19366	0	0
T8	0	8244	0	0
T12	1601872	1582336	0	0
T13	21285	814	0	0
T14	5410	268	0	0
T20	17478	506	0	0
T21	1329324	35708	0	0
T23	4110	56	0	0
T24	191678	2485	0	0
T28	6154	68	0	0
T40	2862	21	0	0
T41	0	52	0	0
T58	2450	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69539019	0	0
T1	740440	128	0	0
T2	7960	256	0	0
T3	5632	260	0	0
T4	980065	252	0	0
T5	14370	142	0	0
T6	337262	31082	0	0
T7	50945	19366	0	0
T8	0	8244	0	0
T12	1601872	1582336	0	0
T13	21285	814	0	0
T14	5410	268	0	0
T20	17478	506	0	0
T21	1329324	35708	0	0
T23	4110	56	0	0
T24	191678	2485	0	0
T28	6154	68	0	0
T40	2862	21	0	0
T41	0	52	0	0
T58	2450	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	324571319	0	0
T1	740440	256	0	0
T2	7960	512	0	0
T3	5632	520	0	0
T4	980065	151631	0	0
T5	14370	3478	0	0
T6	337262	335038	0	0
T7	50945	100902	0	0
T8	0	547543	0	0
T12	1601872	3164672	0	0
T13	21285	1628	0	0
T14	5410	536	0	0
T20	17478	2778	0	0
T21	1329324	120315	0	0
T23	4110	1715	0	0
T24	191678	18173	0	0
T28	6154	7726	0	0
T40	2862	3405	0	0
T41	0	5646	0	0
T58	2450	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	64734216	0	0
T1	740440	128	0	0
T2	7960	256	0	0
T3	5632	260	0	0
T4	784052	0	0	0
T5	9580	128	0	0
T12	1601872	1582336	0	0
T13	17028	814	0	0
T14	4328	268	0	0
T20	11652	464	0	0
T21	886216	34960	0	0
T24	0	2432	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20740	0	6162
T25	978950	1235	0	2
T27	4698	0	0	2
T33	248372	0	0	2
T36	14554	0	0	2
T67	1133232	0	0	2
T68	97040	0	0	2
T75	8236	0	0	2
T87	85338	0	0	2
T96	628016	0	0	2
T99	2548	0	0	2
T117	0	1	0	0
T123	0	22	0	0
T189	0	21	0	0
T191	0	501	0	0
T199	0	531	0	0
T206	0	58	0	0
T207	0	40	0	0
T208	0	515	0	0
T209	0	29	0	0
T210	0	158	0	0
T211	0	31	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1110660	1110612	0	0
T2	11940	11166	0	0
T3	8448	7038	0	0
T4	1176078	1175700	0	0
T5	14370	14058	0	0
T12	2402808	2402706	0	0
T13	25542	21114	0	0
T14	6492	4998	0	0
T20	17478	16494	0	0
T21	1329324	1249512	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1530122724	64735104	0	0
T1	740440	128	0	0
T2	7960	256	0	0
T3	5632	260	0	0
T4	784052	0	0	0
T5	9580	128	0	0
T12	1601872	1582336	0	0
T13	17028	814	0	0
T14	4328	268	0	0
T20	11652	464	0	0
T21	886216	34960	0	0
T24	0	2432	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T23,T6
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T23
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T23
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T25,T51,T189
1	1	Covered	T4,T20,T5

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T20,T5
1	1	0	Covered	T4,T20,T5
1	1	1	Covered	T4,T20,T5

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T20,T5
1	1	0	Covered	T4,T20,T5
1	1	1	Covered	T4,T20,T5

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T20,T5
1	1	0	Covered	T4,T20,T5
1	1	1	Covered	T4,T20,T5

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T20,T5
1	1	0	Covered	T4,T20,T5
1	1	1	Covered	T4,T20,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T20,T5
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T25,T51
1	0	Covered	T6,T25,T51

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T25,T51
1	0	Covered	T4,T20,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T28
1	0	Covered	T4,T20,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T20,T5
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T20,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T20,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T20,T5
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T20,T5
1	1	Covered	T4,T20,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T23,T6,T7
1	0	Covered	T4,T20,T5
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T5
1	0	Covered	T4,T20,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T20,T5

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T20,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T20,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T20,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T20,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382530681	381675063	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	382530681	2552295	0	0
GntImpliesValid_A	382530681	2552295	0	0
GrantKnown_A	382530681	381675063	0	0
IdxKnown_A	382530681	381675063	0	0
IndexIsCorrect_A	382530681	2552295	0	0
LockArbDecision_A	382530681	0	0	0
NoReadyValidNoGrant_A	382530681	272090502	0	0
ReadyAndValidImplyGrant_A	382530681	2552295	0	0
ReqAndReadyImplyGrant_A	382530681	2552295	0	0
ReqImpliesValid_A	382530681	104574223	0	0
ReqStaysHighUntilGranted0_M	382530681	0	0	0
RoundRobin_A	382530681	11013	0	1027
ValidKnown_A	382530681	381675063	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	2552295	0	0
T4	196013	252	0	0
T5	2395	13	0	0
T6	168631	15613	0	0
T7	0	10557	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	41	0	0
T21	221554	748	0	0
T23	2055	51	0	0
T24	95839	33	0	0
T28	0	43	0	0
T40	0	14	0	0
T58	1225	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	2552295	0	0
T4	196013	252	0	0
T5	2395	13	0	0
T6	168631	15613	0	0
T7	0	10557	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	41	0	0
T21	221554	748	0	0
T23	2055	51	0	0
T24	95839	33	0	0
T28	0	43	0	0
T40	0	14	0	0
T58	1225	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	2552295	0	0
T4	196013	252	0	0
T5	2395	13	0	0
T6	168631	15613	0	0
T7	0	10557	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	41	0	0
T21	221554	748	0	0
T23	2055	51	0	0
T24	95839	33	0	0
T28	0	43	0	0
T40	0	14	0	0
T58	1225	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	272090502	0	0
T1	185110	185099	0	0
T2	1990	1797	0	0
T3	1408	1108	0	0
T4	196013	44283	0	0
T5	2395	610	0	0
T12	400468	387184	0	0
T13	4257	3315	0	0
T14	1082	766	0	0
T20	2913	2204	0	0
T21	221554	150909	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	2552295	0	0
T4	196013	252	0	0
T5	2395	13	0	0
T6	168631	15613	0	0
T7	0	10557	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	41	0	0
T21	221554	748	0	0
T23	2055	51	0	0
T24	95839	33	0	0
T28	0	43	0	0
T40	0	14	0	0
T58	1225	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	2552295	0	0
T4	196013	252	0	0
T5	2395	13	0	0
T6	168631	15613	0	0
T7	0	10557	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	41	0	0
T21	221554	748	0	0
T23	2055	51	0	0
T24	95839	33	0	0
T28	0	43	0	0
T40	0	14	0	0
T58	1225	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	104574223	0	0
T4	196013	151631	0	0
T5	2395	1697	0	0
T6	168631	167523	0	0
T7	0	50459	0	0
T13	4257	0	0	0
T14	1082	0	0	0
T20	2913	476	0	0
T21	221554	50395	0	0
T23	2055	886	0	0
T24	95839	6850	0	0
T28	0	2757	0	0
T40	0	2173	0	0
T58	1225	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	11013	0	1027
T25	489475	472	0	1
T27	2349	0	0	1
T33	124186	0	0	1
T36	7277	0	0	1
T67	566616	0	0	1
T68	48520	0	0	1
T75	4118	0	0	1
T87	42669	0	0	1
T96	314008	0	0	1
T99	1274	0	0	1
T117	0	1	0	0
T123	0	4	0	0
T189	0	12	0	0
T191	0	251	0	0
T199	0	250	0	0
T206	0	15	0	0
T207	0	40	0	0
T208	0	452	0	0
T209	0	19	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
TOTAL		52	48	92.31
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	4	4
118	4	4
122	0	4
126	4	4
128	4	4
148	3	3
150	3	3
151	3	3
155	3	3
156	3	3
160	3	3
161	3	3
163	1	1(2 unreachable)
164	3	3
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Covered	Percent
Conditions	130	127	97.69
Logical	130	127	97.69
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T20,T5,T24
1	1	Covered	T20,T5,T24

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T20,T5,T24
1	1	Covered	T20,T5,T24

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T20,T5,T24
1	1	Covered	T20,T5,T24

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T24
1	0	Covered	T25,T189,T191
1	1	Covered	T20,T5,T24

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T24,T23,T6
1	1	0	Covered	T20,T5,T24
1	1	1	Covered	T20,T5,T24

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T20,T5,T24
1	1	0	Covered	T20,T5,T24
1	1	1	Covered	T24,T23,T6

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T20,T5,T24
1	1	0	Covered	T24,T23,T6
1	1	1	Covered	T24,T23,T6

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T20,T5
1	0	1	Covered	T20,T5,T24
1	1	0	Covered	T24,T23,T6
1	1	1	Covered	T24,T23,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T5,T24

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T20,T5,T24
0	1	Covered	T20,T5,T24
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T24
1	0	Covered	T20,T5,T24
1	1	Covered	T20,T5,T24

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T5,T24

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T24,T23,T6
0	1	Covered	T20,T5,T24
1	0	Covered	T20,T5,T24

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T24
1	0	Covered	T24,T23,T6
1	1	Covered	T20,T5,T24

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T5,T24

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T24,T23,T6
0	1	Covered	T24,T23,T6
1	0	Covered	T20,T5,T24

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T24
1	0	Covered	T24,T23,T6
1	1	Covered	T24,T23,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T5,T24

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T24,T23,T6
0	1	Covered	T24,T23,T6
1	0	Covered	T20,T5,T24

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T24
1	0	Covered	T24,T23,T6
1	1	Covered	T24,T23,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T20,T5,T24
0	1	Covered	T24,T23,T6
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T24,T23,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T20,T5,T24
0	1	Covered	T20,T5,T24
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T5,T24

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T20,T5,T24
0	1	Covered	T24,T23,T6
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T24,T23,T6

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T25
1	0	Covered	T6,T25,T51

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T5,T24
1	0	Covered	T24,T23,T6

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T23,T6
1	0	Covered	T20,T5,T24

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T25,T51
1	0	Covered	T24,T23,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T8
1	0	Covered	T20,T5,T24

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T5,T24
1	0	Covered	T24,T23,T6

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T5,T24
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T5,T24
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T20,T5,T24
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T5,T24
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T20,T5,T24
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T20,T5,T24
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T20,T5,T24

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T23,T6
1	0	Covered	T20,T5,T24
1	1	Covered	T20,T5,T24

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T5,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T24,T23,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T20,T5,T24
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T20,T5,T24
1	1	Covered	T20,T5,T24

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T24,T23,T6
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T5,T24
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T20,T5,T24
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T23,T6
1	0	Covered	T20,T5,T24

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T5,T24

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T5,T24

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T5,T24

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T5,T24

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T5,T24

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T20,T5,T24

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T5,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T5,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T5,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T5,T24
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382530681	381675063	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	382530681	2251620	0	0
GntImpliesValid_A	382530681	2251620	0	0
GrantKnown_A	382530681	381675063	0	0
IdxKnown_A	382530681	381675063	0	0
IndexIsCorrect_A	382530681	2251620	0	0
LockArbDecision_A	382530681	0	0	0
NoReadyValidNoGrant_A	382530681	286661532	0	0
ReadyAndValidImplyGrant_A	382530681	2251620	0	0
ReqAndReadyImplyGrant_A	382530681	2251620	0	0
ReqImpliesValid_A	382530681	90526698	0	0
ReqStaysHighUntilGranted0_M	382530681	0	0	0
RoundRobin_A	382530681	9727	0	1027
ValidKnown_A	382530681	381675063	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	2251620	0	0
T5	2395	1	0	0
T6	168631	15469	0	0
T7	50945	8809	0	0
T8	0	8244	0	0
T20	2913	1	0	0
T21	221554	0	0	0
T23	2055	5	0	0
T24	95839	20	0	0
T28	6154	25	0	0
T40	2862	7	0	0
T41	0	52	0	0
T58	1225	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	2251620	0	0
T5	2395	1	0	0
T6	168631	15469	0	0
T7	50945	8809	0	0
T8	0	8244	0	0
T20	2913	1	0	0
T21	221554	0	0	0
T23	2055	5	0	0
T24	95839	20	0	0
T28	6154	25	0	0
T40	2862	7	0	0
T41	0	52	0	0
T58	1225	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	2251620	0	0
T5	2395	1	0	0
T6	168631	15469	0	0
T7	50945	8809	0	0
T8	0	8244	0	0
T20	2913	1	0	0
T21	221554	0	0	0
T23	2055	5	0	0
T24	95839	20	0	0
T28	6154	25	0	0
T40	2862	7	0	0
T41	0	52	0	0
T58	1225	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	286661532	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	814	0	0
T12	400468	387344	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	1371	0	0
T21	221554	208252	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	2251620	0	0
T5	2395	1	0	0
T6	168631	15469	0	0
T7	50945	8809	0	0
T8	0	8244	0	0
T20	2913	1	0	0
T21	221554	0	0	0
T23	2055	5	0	0
T24	95839	20	0	0
T28	6154	25	0	0
T40	2862	7	0	0
T41	0	52	0	0
T58	1225	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	2251620	0	0
T5	2395	1	0	0
T6	168631	15469	0	0
T7	50945	8809	0	0
T8	0	8244	0	0
T20	2913	1	0	0
T21	221554	0	0	0
T23	2055	5	0	0
T24	95839	20	0	0
T28	6154	25	0	0
T40	2862	7	0	0
T41	0	52	0	0
T58	1225	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	90526698	0	0
T5	2395	1525	0	0
T6	168631	167515	0	0
T7	50945	50443	0	0
T8	0	547543	0	0
T20	2913	1374	0	0
T21	221554	0	0	0
T23	2055	829	0	0
T24	95839	6459	0	0
T28	6154	4969	0	0
T40	2862	1232	0	0
T41	0	5646	0	0
T58	1225	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	9727	0	1027
T25	489475	763	0	1
T27	2349	0	0	1
T33	124186	0	0	1
T36	7277	0	0	1
T67	566616	0	0	1
T68	48520	0	0	1
T75	4118	0	0	1
T87	42669	0	0	1
T96	314008	0	0	1
T99	1274	0	0	1
T123	0	18	0	0
T189	0	9	0	0
T191	0	250	0	0
T199	0	281	0	0
T206	0	43	0	0
T208	0	63	0	0
T209	0	10	0	0
T210	0	158	0	0
T211	0	31	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	46	90.20
Logical	51	46	90.20
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T115
1	0	1	Not Covered
1	1	0	Covered	T12,T20,T23
1	1	1	Covered	T12,T20,T23

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T12,T20,T23
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T116
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T20,T23

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382530681	381675063	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	382530681	15661944	0	0
GntImpliesValid_A	382530681	15661944	0	0
GrantKnown_A	382530681	381675063	0	0
IdxKnown_A	382530681	381675063	0	0
IndexIsCorrect_A	382530681	15661944	0	0
LockArbDecision_A	382490122	15661901	0	0
NoReadyValidNoGrant_A	382530681	350351060	0	0
ReadyAndValidImplyGrant_A	382530681	15661944	0	0
ReqAndReadyImplyGrant_A	382530681	15661944	0	0
ReqImpliesValid_A	382530681	31323965	0	0
ReqStaysHighUntilGranted0_M	382483227	15661827	0	0
RoundRobin_A	382530681	0	0	1027
ValidKnown_A	382530681	381675063	0	0
gen_data_port_assertion.DataFlow_A	382530681	15661944	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661944	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661944	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661944	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382490122	15661901	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	350351060	0	0
T1	185110	185096	0	0
T2	1990	1733	0	0
T3	1408	1043	0	0
T4	196013	195950	0	0
T5	2395	2279	0	0
T12	400468	321335	0	0
T13	4257	3113	0	0
T14	1082	699	0	0
T20	2913	2517	0	0
T21	221554	190772	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661944	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661944	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	31323965	0	0
T1	185110	64	0	0
T2	1990	128	0	0
T3	1408	130	0	0
T4	196013	0	0	0
T5	2395	64	0	0
T12	400468	791168	0	0
T13	4257	406	0	0
T14	1082	134	0	0
T20	2913	232	0	0
T21	221554	17480	0	0
T24	0	1216	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	382483227	15661827	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	0	0	1027

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661944	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		25	25	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	51	48	94.12
Logical	51	48	94.12
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T115
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T115
1	1	0	Covered	T12,T20,T23
1	1	1	Covered	T12,T20,T23

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T12,T20,T23
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T115
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T115
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T20,T23

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382530681	381675063	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	382530681	15661982	0	0
GntImpliesValid_A	382530681	15661982	0	0
GrantKnown_A	382530681	381675063	0	0
IdxKnown_A	382530681	381675063	0	0
IndexIsCorrect_A	382530681	15661982	0	0
LockArbDecision_A	382490122	15661901	0	0
NoReadyValidNoGrant_A	382530681	350351093	0	0
ReadyAndValidImplyGrant_A	382530681	15661982	0	0
ReqAndReadyImplyGrant_A	382530681	15661982	0	0
ReqImpliesValid_A	382530681	31323970	0	0
ReqStaysHighUntilGranted0_M	382483227	15661827	0	0
RoundRobin_A	382530681	0	0	1027
ValidKnown_A	382530681	381675063	0	0
gen_data_port_assertion.DataFlow_A	382530681	15661982	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661982	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661982	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661982	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382490122	15661901	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	350351093	0	0
T1	185110	185096	0	0
T2	1990	1733	0	0
T3	1408	1043	0	0
T4	196013	195950	0	0
T5	2395	2279	0	0
T12	400468	321335	0	0
T13	4257	3113	0	0
T14	1082	699	0	0
T20	2913	2517	0	0
T21	221554	190772	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661982	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661982	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	31323970	0	0
T1	185110	64	0	0
T2	1990	128	0	0
T3	1408	130	0	0
T4	196013	0	0	0
T5	2395	64	0	0
T12	400468	791168	0	0
T13	4257	406	0	0
T14	1082	134	0	0
T20	2913	232	0	0
T21	221554	17480	0	0
T24	0	1216	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	382483227	15661827	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	0	0	1027

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	15661982	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	203	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126		unreachable
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T6,T7,T55
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable	T205
1	0	1	Unreachable	T6,T7,T55
1	1	0	Covered	T12,T20,T23
1	1	1	Unreachable	T12,T20,T23

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T23
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T12,T20,T23
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T55
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T20,T23

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382530681	381675063	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	382530681	16705572	0	0
GntImpliesValid_A	382530681	16705572	0	0
GrantKnown_A	382530681	381675063	0	0
IdxKnown_A	382530681	381675063	0	0
IndexIsCorrect_A	382530681	16705572	0	0
LockArbDecision_A	382530518	16705567	0	0
NoReadyValidNoGrant_A	382530681	348263787	0	0
ReadyAndValidImplyGrant_A	382530681	16705572	0	0
ReqAndReadyImplyGrant_A	382530681	16705572	0	0
ReqImpliesValid_A	382530681	33411242	0	0
ReqStaysHighUntilGranted0_M	382435207	16705281	0	0
RoundRobin_A	382530681	0	0	1027
ValidKnown_A	382530681	381675063	0	0
gen_data_port_assertion.DataFlow_A	382530681	16705572	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705572	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705572	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705572	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530518	16705567	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	348263787	0	0
T1	185110	185096	0	0
T2	1990	1733	0	0
T3	1408	1043	0	0
T4	196013	195950	0	0
T5	2395	2279	0	0
T12	400468	321335	0	0
T13	4257	3111	0	0
T14	1082	699	0	0
T20	2913	2517	0	0
T21	221554	190772	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705572	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705572	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	33411242	0	0
T1	185110	64	0	0
T2	1990	128	0	0
T3	1408	130	0	0
T4	196013	0	0	0
T5	2395	64	0	0
T12	400468	791168	0	0
T13	4257	408	0	0
T14	1082	134	0	0
T20	2913	232	0	0
T21	221554	17480	0	0
T24	0	1216	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	382435207	16705281	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	0	0	1027

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705572	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	0	0
CONT_ASSIGN	126	0	0
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	2	2
118	2	2
122	2	2
126		unreachable
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Covered	Percent
Conditions	43	42	97.67
Logical	43	42	97.67
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T6,T7,T55
1	1	0	Covered	T1,T2,T3
1	1	1	Unreachable	T1,T2,T3

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Unreachable	T6,T7,T55
1	1	0	Covered	T12,T20,T23
1	1	1	Unreachable	T12,T20,T23

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T23
1	0	Unreachable	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T12,T20,T23
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable	T12,T20,T23
1	1	Covered	T12,T20,T23

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T55
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T20,T23

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T20,T23
1	0	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T23

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

---

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382530681	381675063	0	0
CheckNGreaterZero_A	1032	1032	0	0
GntImpliesReady_A	382530681	16705606	0	0
GntImpliesValid_A	382530681	16705606	0	0
GrantKnown_A	382530681	381675063	0	0
IdxKnown_A	382530681	381675063	0	0
IndexIsCorrect_A	382530681	16705606	0	0
LockArbDecision_A	382530518	16705567	0	0
NoReadyValidNoGrant_A	382530681	348263842	0	0
ReadyAndValidImplyGrant_A	382530681	16705606	0	0
ReqAndReadyImplyGrant_A	382530681	16705606	0	0
ReqImpliesValid_A	382530681	33411221	0	0
ReqStaysHighUntilGranted0_M	382435207	16705281	0	0
RoundRobin_A	382530681	0	0	1027
ValidKnown_A	382530681	381675063	0	0
gen_data_port_assertion.DataFlow_A	382530681	16705606	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032	1032	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705606	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705606	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705606	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530518	16705567	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	348263842	0	0
T1	185110	185096	0	0
T2	1990	1733	0	0
T3	1408	1043	0	0
T4	196013	195950	0	0
T5	2395	2279	0	0
T12	400468	321335	0	0
T13	4257	3111	0	0
T14	1082	699	0	0
T20	2913	2517	0	0
T21	221554	190772	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705606	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705606	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	33411221	0	0
T1	185110	64	0	0
T2	1990	128	0	0
T3	1408	130	0	0
T4	196013	0	0	0
T5	2395	64	0	0
T12	400468	791168	0	0
T13	4257	408	0	0
T14	1082	134	0	0
T20	2913	232	0	0
T21	221554	17480	0	0
T24	0	1216	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	382435207	16705281	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	0	0	1027

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	381675063	0	0
T1	185110	185102	0	0
T2	1990	1861	0	0
T3	1408	1173	0	0
T4	196013	195950	0	0
T5	2395	2343	0	0
T12	400468	400451	0	0
T13	4257	3519	0	0
T14	1082	833	0	0
T20	2913	2749	0	0
T21	221554	208252	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382530681	16705606	0	0
T1	185110	32	0	0
T2	1990	64	0	0
T3	1408	65	0	0
T4	196013	0	0	0
T5	2395	32	0	0
T12	400468	395584	0	0
T13	4257	204	0	0
T14	1082	67	0	0
T20	2913	116	0	0
T21	221554	8740	0	0
T24	0	608	0	0