Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23307701	1		T1	278		T2	188		T3	387
full_word	7598090	1		T1	71		T2	59		T3	164

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30905471	1		T1	349		T2	247		T3	551
auto[TlIntgErrCmd]	117	1		T206	7		T208	5		T209	10
auto[TlIntgErrData]	102	1		T206	9		T208	6		T209	5
auto[TlIntgErrBoth]	101	1		T206	4		T208	9		T209	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26517263	1		T1	277		T2	187		T3	455
auto[1]	4388528	1		T1	72		T2	60		T3	96

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22664996	1		T1	273		T2	183		T3	365
auto[TlIntgErrNone]	partial	auto[1]	642419	1		T1	5		T2	5		T3	22
auto[TlIntgErrNone]	full_word	auto[0]	3852118	1		T1	4		T2	4		T3	90
auto[TlIntgErrNone]	full_word	auto[1]	3745938	1		T1	67		T2	55		T3	74
auto[TlIntgErrCmd]	partial	auto[0]	46	1		T206	3		T208	2		T209	2
auto[TlIntgErrCmd]	partial	auto[1]	62	1		T206	3		T208	3		T209	8
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T270	1		T386	1		T390	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T206	1		T391	1		T388	1
auto[TlIntgErrData]	partial	auto[0]	51	1		T206	4		T208	1		T209	3
auto[TlIntgErrData]	partial	auto[1]	38	1		T206	5		T208	4		T209	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T270	1		T388	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	11	1		T208	1		T209	1		T265	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T206	1		T208	3		T209	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T206	2		T208	5		T209	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1		T206	1		T208	1		T265	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T386	1		T392	1		T393	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22882	1		T114	537		T111	276		T112	121
full_word	4049189	1		T3	7		T5	16522		T6	16875

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4071765	1		T3	7		T5	16522		T6	16875
auto[TlIntgErrCmd]	97	1		T206	6		T208	4		T209	4
auto[TlIntgErrData]	118	1		T206	10		T208	7		T209	7
auto[TlIntgErrBoth]	91	1		T206	4		T208	7		T209	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4043753	1		T3	7		T5	16522		T6	16875
auto[1]	28318	1		T114	629		T111	334		T112	160

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1449	1		T114	23		T111	8		T112	10
auto[TlIntgErrNone]	partial	auto[1]	21160	1		T114	514		T111	268		T112	111
auto[TlIntgErrNone]	full_word	auto[0]	4042177	1		T3	7		T5	16522		T6	16875
auto[TlIntgErrNone]	full_word	auto[1]	6979	1		T114	115		T111	66		T112	49
auto[TlIntgErrCmd]	partial	auto[0]	28	1		T206	1		T208	1		T209	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T206	4		T208	2		T209	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T383	2		T274	1		T394	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1		T206	1		T208	1		T265	1
auto[TlIntgErrData]	partial	auto[0]	60	1		T206	9		T208	3		T209	4
auto[TlIntgErrData]	partial	auto[1]	46	1		T208	3		T209	3		T270	4
auto[TlIntgErrData]	full_word	auto[0]	4	1		T394	1		T386	1		T392	1
auto[TlIntgErrData]	full_word	auto[1]	8	1		T206	1		T208	1		T274	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T206	2		T208	1		T209	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T206	2		T208	5		T209	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T274	1		T386	1		T391	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T208	1		T209	1		T387	1