Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1468849036	1465530160	0	0
CheckNGreaterZero_A	4180	4180	0	0
GntImpliesReady_A	1468849036	401323081	0	0
GntImpliesValid_A	1468849036	401323081	0	0
GrantKnown_A	1468849036	1465530160	0	0
IdxKnown_A	1468849036	1465530160	0	0
IndexIsCorrect_A	1468849036	401323081	0	0
NoReadyValidNoGrant_A	1468849036	172169363	0	0
Priority_A	1468849036	426202258	0	0
ReadyAndValidImplyGrant_A	1468849036	401323081	0	0
ReqAndReadyImplyGrant_A	1468849036	401323081	0	0
ReqImpliesValid_A	1468849036	426202258	0	0
ValidKnown_A	1468849036	1465530160	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	1465530160	0	0
T1	7780	7440	0	0
T2	4184	3808	0	0
T3	8748	8260	0	0
T4	1146172	1077616	0	0
T5	278152	277568	0	0
T11	1543244	1543188	0	0
T16	4528	4196	0	0
T17	10672	10304	0	0
T18	3384	3184	0	0
T19	8712	8364	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4180	4180	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T11	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	401323081	0	0
T1	7780	952	0	0
T2	4184	544	0	0
T3	8748	432	0	0
T4	1146172	355360	0	0
T5	278152	48766	0	0
T6	0	17956	0	0
T11	1543244	514652	0	0
T12	0	826612	0	0
T16	4528	64	0	0
T17	10672	2734	0	0
T18	3384	66	0	0
T19	8712	952	0	0
T26	0	1662496	0	0
T64	0	17312	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	401323081	0	0
T1	7780	952	0	0
T2	4184	544	0	0
T3	8748	432	0	0
T4	1146172	355360	0	0
T5	278152	48766	0	0
T6	0	17956	0	0
T11	1543244	514652	0	0
T12	0	826612	0	0
T16	4528	64	0	0
T17	10672	2734	0	0
T18	3384	66	0	0
T19	8712	952	0	0
T26	0	1662496	0	0
T64	0	17312	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	1465530160	0	0
T1	7780	7440	0	0
T2	4184	3808	0	0
T3	8748	8260	0	0
T4	1146172	1077616	0	0
T5	278152	277568	0	0
T11	1543244	1543188	0	0
T16	4528	4196	0	0
T17	10672	10304	0	0
T18	3384	3184	0	0
T19	8712	8364	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	1465530160	0	0
T1	7780	7440	0	0
T2	4184	3808	0	0
T3	8748	8260	0	0
T4	1146172	1077616	0	0
T5	278152	277568	0	0
T11	1543244	1543188	0	0
T16	4528	4196	0	0
T17	10672	10304	0	0
T18	3384	3184	0	0
T19	8712	8364	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	401323081	0	0
T1	7780	952	0	0
T2	4184	544	0	0
T3	8748	432	0	0
T4	1146172	355360	0	0
T5	278152	48766	0	0
T6	0	17956	0	0
T11	1543244	514652	0	0
T12	0	826612	0	0
T16	4528	64	0	0
T17	10672	2734	0	0
T18	3384	66	0	0
T19	8712	952	0	0
T26	0	1662496	0	0
T64	0	17312	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	172169363	0	0
T1	3890	256	0	0
T2	2092	256	0	0
T3	8748	914	0	0
T4	1146172	85040	0	0
T5	278152	140040	0	0
T6	85446	23364	0	0
T7	0	348	0	0
T11	1543244	2109952	0	0
T12	337040	1048888	0	0
T16	4528	256	0	0
T17	10672	330	0	0
T18	3384	264	0	0
T19	8712	256	0	0
T26	0	1748	0	0
T45	0	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	426202258	0	0
T1	7780	952	0	0
T2	4184	544	0	0
T3	8748	432	0	0
T4	1146172	355360	0	0
T5	278152	51882	0	0
T6	0	30184	0	0
T11	1543244	514652	0	0
T12	0	826612	0	0
T16	4528	64	0	0
T17	10672	2734	0	0
T18	3384	66	0	0
T19	8712	952	0	0
T26	0	1662496	0	0
T64	0	17312	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	401323081	0	0
T1	7780	952	0	0
T2	4184	544	0	0
T3	8748	432	0	0
T4	1146172	355360	0	0
T5	278152	48766	0	0
T6	0	17956	0	0
T11	1543244	514652	0	0
T12	0	826612	0	0
T16	4528	64	0	0
T17	10672	2734	0	0
T18	3384	66	0	0
T19	8712	952	0	0
T26	0	1662496	0	0
T64	0	17312	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	401323081	0	0
T1	7780	952	0	0
T2	4184	544	0	0
T3	8748	432	0	0
T4	1146172	355360	0	0
T5	278152	48766	0	0
T6	0	17956	0	0
T11	1543244	514652	0	0
T12	0	826612	0	0
T16	4528	64	0	0
T17	10672	2734	0	0
T18	3384	66	0	0
T19	8712	952	0	0
T26	0	1662496	0	0
T64	0	17312	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	426202258	0	0
T1	7780	952	0	0
T2	4184	544	0	0
T3	8748	432	0	0
T4	1146172	355360	0	0
T5	278152	51882	0	0
T6	0	30184	0	0
T11	1543244	514652	0	0
T12	0	826612	0	0
T16	4528	64	0	0
T17	10672	2734	0	0
T18	3384	66	0	0
T19	8712	952	0	0
T26	0	1662496	0	0
T64	0	17312	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1468849036	1465530160	0	0
T1	7780	7440	0	0
T2	4184	3808	0	0
T3	8748	8260	0	0
T4	1146172	1077616	0	0
T5	278152	277568	0	0
T11	1543244	1543188	0	0
T16	4528	4196	0	0
T17	10672	10304	0	0
T18	3384	3184	0	0
T19	8712	8364	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	367212259	366382540	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	367212259	107828999	0	0
GntImpliesValid_A	367212259	107828999	0	0
GrantKnown_A	367212259	366382540	0	0
IdxKnown_A	367212259	366382540	0	0
IndexIsCorrect_A	367212259	107828999	0	0
NoReadyValidNoGrant_A	367212259	44987614	0	0
Priority_A	367212259	114078511	0	0
ReadyAndValidImplyGrant_A	367212259	107828999	0	0
ReqAndReadyImplyGrant_A	367212259	107828999	0	0
ReqImpliesValid_A	367212259	114078511	0	0
ValidKnown_A	367212259	366382540	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	107828999	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	15908	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	107828999	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	15908	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	107828999	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	15908	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	44987614	0	0
T1	1945	128	0	0
T2	1046	128	0	0
T3	2187	447	0	0
T4	286543	42520	0	0
T5	69538	44231	0	0
T11	385811	530688	0	0
T16	1132	128	0	0
T17	2668	144	0	0
T18	846	128	0	0
T19	2178	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	114078511	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	16211	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	107828999	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	15908	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	107828999	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	15908	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	114078511	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	16211	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	367212259	366382540	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	367212259	107829130	0	0
GntImpliesValid_A	367212259	107829130	0	0
GrantKnown_A	367212259	366382540	0	0
IdxKnown_A	367212259	366382540	0	0
IndexIsCorrect_A	367212259	107829130	0	0
NoReadyValidNoGrant_A	367212259	44987605	0	0
Priority_A	367212259	114078651	0	0
ReadyAndValidImplyGrant_A	367212259	107829130	0	0
ReqAndReadyImplyGrant_A	367212259	107829130	0	0
ReqImpliesValid_A	367212259	114078651	0	0
ValidKnown_A	367212259	366382540	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	107829130	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	15908	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	107829130	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	15908	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	107829130	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	15908	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	44987605	0	0
T1	1945	128	0	0
T2	1046	128	0	0
T3	2187	447	0	0
T4	286543	42520	0	0
T5	69538	44231	0	0
T11	385811	530688	0	0
T16	1132	128	0	0
T17	2668	144	0	0
T18	846	128	0	0
T19	2178	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	114078651	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	16211	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	107829130	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	15908	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	107829130	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	15908	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	114078651	0	0
T1	1945	32	0	0
T2	1046	272	0	0
T3	2187	146	0	0
T4	286543	177680	0	0
T5	69538	16211	0	0
T11	385811	129429	0	0
T16	1132	32	0	0
T17	2668	801	0	0
T18	846	32	0	0
T19	2178	476	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T17
1	0	Covered	T3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T3,T17
1	1	Covered	T3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T3,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	367212259	366382540	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	367212259	92832519	0	0
GntImpliesValid_A	367212259	92832519	0	0
GrantKnown_A	367212259	366382540	0	0
IdxKnown_A	367212259	366382540	0	0
IndexIsCorrect_A	367212259	92832519	0	0
NoReadyValidNoGrant_A	367212259	41097072	0	0
Priority_A	367212259	99022591	0	0
ReadyAndValidImplyGrant_A	367212259	92832519	0	0
ReqAndReadyImplyGrant_A	367212259	92832519	0	0
ReqImpliesValid_A	367212259	99022591	0	0
ValidKnown_A	367212259	366382540	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	92832519	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	8475	0	0
T6	0	8978	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	92832519	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	8475	0	0
T6	0	8978	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	92832519	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	8475	0	0
T6	0	8978	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	41097072	0	0
T3	2187	10	0	0
T4	286543	0	0	0
T5	69538	25789	0	0
T6	42723	11682	0	0
T7	0	174	0	0
T11	385811	524288	0	0
T12	168520	524444	0	0
T16	1132	0	0	0
T17	2668	21	0	0
T18	846	4	0	0
T19	2178	0	0	0
T26	0	874	0	0
T45	0	64	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	99022591	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	9730	0	0
T6	0	15092	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	92832519	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	8475	0	0
T6	0	8978	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	92832519	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	8475	0	0
T6	0	8978	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	99022591	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	9730	0	0
T6	0	15092	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T17
1	0	Covered	T3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T3,T17
1	1	Covered	T3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T3,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	367212259	366382540	0	0
CheckNGreaterZero_A	1045	1045	0	0
GntImpliesReady_A	367212259	92832433	0	0
GntImpliesValid_A	367212259	92832433	0	0
GrantKnown_A	367212259	366382540	0	0
IdxKnown_A	367212259	366382540	0	0
IndexIsCorrect_A	367212259	92832433	0	0
NoReadyValidNoGrant_A	367212259	41097072	0	0
Priority_A	367212259	99022505	0	0
ReadyAndValidImplyGrant_A	367212259	92832433	0	0
ReqAndReadyImplyGrant_A	367212259	92832433	0	0
ReqImpliesValid_A	367212259	99022505	0	0
ValidKnown_A	367212259	366382540	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045	1045	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	92832433	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	8475	0	0
T6	0	8978	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	92832433	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	8475	0	0
T6	0	8978	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	92832433	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	8475	0	0
T6	0	8978	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	41097072	0	0
T3	2187	10	0	0
T4	286543	0	0	0
T5	69538	25789	0	0
T6	42723	11682	0	0
T7	0	174	0	0
T11	385811	524288	0	0
T12	168520	524444	0	0
T16	1132	0	0	0
T17	2668	21	0	0
T18	846	4	0	0
T19	2178	0	0	0
T26	0	874	0	0
T45	0	64	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	99022505	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	9730	0	0
T6	0	15092	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	92832433	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	8475	0	0
T6	0	8978	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	92832433	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	8475	0	0
T6	0	8978	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	99022505	0	0
T1	1945	444	0	0
T2	1046	0	0	0
T3	2187	70	0	0
T4	286543	0	0	0
T5	69538	9730	0	0
T6	0	15092	0	0
T11	385811	127897	0	0
T12	0	413306	0	0
T16	1132	0	0	0
T17	2668	566	0	0
T18	846	1	0	0
T19	2178	0	0	0
T26	0	831248	0	0
T64	0	8656	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367212259	366382540	0	0
T1	1945	1860	0	0
T2	1046	952	0	0
T3	2187	2065	0	0
T4	286543	269404	0	0
T5	69538	69392	0	0
T11	385811	385797	0	0
T16	1132	1049	0	0
T17	2668	2576	0	0
T18	846	796	0	0
T19	2178	2091	0	0