Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.54 100.00 90.15 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.54 100.00 90.15 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.54 100.00 90.15 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.54 100.00 90.15 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.37 100.00 89.50 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.37 100.00 89.50 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.37 100.00 89.50 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.37 100.00 89.50 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Module : flash_phy_rd_buffers
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT3,T5,T4
10CoveredT1,T2,T3
11CoveredT12,T89,T90

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T12,T26

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T4

Branch Coverage for Module : flash_phy_rd_buffers
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T12,T89,T90
0 0 1 - - Covered T4,T12,T26
0 0 0 1 - Covered T3,T5,T4
0 0 0 0 1 Covered T3,T5,T4
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd_buffers
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 2147483647 5199072 0 0
UpdateCheck_A 2147483647 5199060 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5199072 0 0
T3 17496 47 0 0
T4 2292344 2536 0 0
T5 556304 21002 0 0
T6 341784 18770 0 0
T7 0 41 0 0
T11 3086488 0 0 0
T12 1348160 137 0 0
T16 9056 0 0 0
T17 21344 14 0 0
T18 6768 1 0 0
T19 17424 0 0 0
T26 0 1146 0 0
T29 0 5 0 0
T40 0 86 0 0
T45 0 78 0 0
T49 0 2520 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5199060 0 0
T3 17496 47 0 0
T4 2292344 2536 0 0
T5 556304 21002 0 0
T6 341784 18770 0 0
T7 0 41 0 0
T11 3086488 0 0 0
T12 1348160 137 0 0
T16 9056 0 0 0
T17 21344 14 0 0
T18 6768 1 0 0
T19 17424 0 0 0
T26 0 1146 0 0
T29 0 5 0 0
T40 0 86 0 0
T45 0 78 0 0
T49 0 2520 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT3,T5,T4
10CoveredT1,T2,T3
11CoveredT12,T90,T91

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T12,T26

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T12,T90,T91
0 0 1 - - Covered T4,T12,T26
0 0 0 1 - Covered T3,T5,T4
0 0 0 0 1 Covered T3,T5,T4
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 367212259 694508 0 0
UpdateCheck_A 367212259 694504 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 694508 0 0
T3 2187 11 0 0
T4 286543 634 0 0
T5 69538 3130 0 0
T6 42723 2522 0 0
T7 0 4 0 0
T11 385811 0 0 0
T12 168520 21 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 214 0 0
T45 0 14 0 0
T49 0 630 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 694504 0 0
T3 2187 11 0 0
T4 286543 634 0 0
T5 69538 3130 0 0
T6 42723 2522 0 0
T7 0 4 0 0
T11 385811 0 0 0
T12 168520 21 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 214 0 0
T45 0 14 0 0
T49 0 630 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT3,T5,T4
10CoveredT1,T2,T3
11CoveredT12,T90,T92

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T12,T26

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T12,T90,T92
0 0 1 - - Covered T4,T12,T26
0 0 0 1 - Covered T3,T5,T4
0 0 0 0 1 Covered T3,T5,T4
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 367212259 694372 0 0
UpdateCheck_A 367212259 694371 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 694372 0 0
T3 2187 11 0 0
T4 286543 634 0 0
T5 69538 3127 0 0
T6 42723 2513 0 0
T7 0 4 0 0
T11 385811 0 0 0
T12 168520 21 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 213 0 0
T45 0 14 0 0
T49 0 630 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 694371 0 0
T3 2187 11 0 0
T4 286543 634 0 0
T5 69538 3127 0 0
T6 42723 2513 0 0
T7 0 4 0 0
T11 385811 0 0 0
T12 168520 21 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 213 0 0
T45 0 14 0 0
T49 0 630 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT3,T5,T4
10CoveredT1,T2,T3
11CoveredT12,T90,T92

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T12,T26

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T12,T90,T92
0 0 1 - - Covered T4,T12,T26
0 0 0 1 - Covered T3,T5,T4
0 0 0 0 1 Covered T3,T5,T4
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 367212259 694103 0 0
UpdateCheck_A 367212259 694101 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 694103 0 0
T3 2187 11 0 0
T4 286543 634 0 0
T5 69538 3133 0 0
T6 42723 2514 0 0
T7 0 4 0 0
T11 385811 0 0 0
T12 168520 20 0 0
T16 1132 0 0 0
T17 2668 1 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 213 0 0
T45 0 14 0 0
T49 0 630 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 694101 0 0
T3 2187 11 0 0
T4 286543 634 0 0
T5 69538 3133 0 0
T6 42723 2514 0 0
T7 0 4 0 0
T11 385811 0 0 0
T12 168520 20 0 0
T16 1132 0 0 0
T17 2668 1 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 213 0 0
T45 0 14 0 0
T49 0 630 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT3,T5,T4
10CoveredT1,T2,T3
11CoveredT12,T90,T92

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T4

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T12,T26

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T4

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T4

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T12,T90,T92
0 0 1 - - Covered T4,T12,T26
0 0 0 1 - Covered T3,T5,T4
0 0 0 0 1 Covered T3,T5,T4
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 367212259 693758 0 0
UpdateCheck_A 367212259 693757 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 693758 0 0
T3 2187 10 0 0
T4 286543 634 0 0
T5 69538 3137 0 0
T6 42723 2516 0 0
T7 0 3 0 0
T11 385811 0 0 0
T12 168520 20 0 0
T16 1132 0 0 0
T17 2668 1 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 213 0 0
T45 0 13 0 0
T49 0 630 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 693757 0 0
T3 2187 10 0 0
T4 286543 634 0 0
T5 69538 3137 0 0
T6 42723 2516 0 0
T7 0 3 0 0
T11 385811 0 0 0
T12 168520 20 0 0
T16 1132 0 0 0
T17 2668 1 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 213 0 0
T45 0 13 0 0
T49 0 630 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT3,T5,T17
10CoveredT1,T2,T3
11CoveredT12,T89,T90

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T17

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT26,T7,T93

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T17

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T17

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T12,T89,T90
0 0 1 - - Covered T26,T7,T93
0 0 0 1 - Covered T3,T5,T17
0 0 0 0 1 Covered T3,T5,T17
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 367212259 605771 0 0
UpdateCheck_A 367212259 605770 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 605771 0 0
T3 2187 1 0 0
T4 286543 0 0 0
T5 69538 2119 0 0
T6 42723 2176 0 0
T7 0 7 0 0
T11 385811 0 0 0
T12 168520 14 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 1 0 0
T19 2178 0 0 0
T26 0 74 0 0
T40 0 23 0 0
T45 0 6 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 605770 0 0
T3 2187 1 0 0
T4 286543 0 0 0
T5 69538 2119 0 0
T6 42723 2176 0 0
T7 0 7 0 0
T11 385811 0 0 0
T12 168520 14 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 1 0 0
T19 2178 0 0 0
T26 0 74 0 0
T40 0 23 0 0
T45 0 6 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT3,T5,T17
10CoveredT1,T2,T3
11CoveredT12,T89,T90

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T17

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT26,T7,T93

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T17

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T17

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T12,T89,T90
0 0 1 - - Covered T26,T7,T93
0 0 0 1 - Covered T3,T5,T17
0 0 0 0 1 Covered T3,T5,T17
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 367212259 605712 0 0
UpdateCheck_A 367212259 605710 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 605712 0 0
T3 2187 1 0 0
T4 286543 0 0 0
T5 69538 2119 0 0
T6 42723 2182 0 0
T7 0 7 0 0
T11 385811 0 0 0
T12 168520 14 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 73 0 0
T29 0 2 0 0
T40 0 21 0 0
T45 0 6 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 605710 0 0
T3 2187 1 0 0
T4 286543 0 0 0
T5 69538 2119 0 0
T6 42723 2182 0 0
T7 0 7 0 0
T11 385811 0 0 0
T12 168520 14 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 73 0 0
T29 0 2 0 0
T40 0 21 0 0
T45 0 6 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT3,T5,T17
10CoveredT1,T2,T3
11CoveredT12,T89,T90

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T17

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT26,T7,T93

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T17

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T17

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T12,T89,T90
0 0 1 - - Covered T26,T7,T93
0 0 0 1 - Covered T3,T5,T17
0 0 0 0 1 Covered T3,T5,T17
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 367212259 605534 0 0
UpdateCheck_A 367212259 605533 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 605534 0 0
T3 2187 1 0 0
T4 286543 0 0 0
T5 69538 2119 0 0
T6 42723 2170 0 0
T7 0 6 0 0
T11 385811 0 0 0
T12 168520 14 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 73 0 0
T29 0 2 0 0
T40 0 22 0 0
T45 0 6 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 605533 0 0
T3 2187 1 0 0
T4 286543 0 0 0
T5 69538 2119 0 0
T6 42723 2170 0 0
T7 0 6 0 0
T11 385811 0 0 0
T12 168520 14 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 73 0 0
T29 0 2 0 0
T40 0 22 0 0
T45 0 6 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT3,T5,T17
10CoveredT1,T2,T3
11CoveredT12,T89,T90

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T17

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT26,T7,T93

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T17

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T5,T17

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T12,T89,T90
0 0 1 - - Covered T26,T7,T93
0 0 0 1 - Covered T3,T5,T17
0 0 0 0 1 Covered T3,T5,T17
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 367212259 605314 0 0
UpdateCheck_A 367212259 605314 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 605314 0 0
T3 2187 1 0 0
T4 286543 0 0 0
T5 69538 2118 0 0
T6 42723 2177 0 0
T7 0 6 0 0
T11 385811 0 0 0
T12 168520 13 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 73 0 0
T29 0 1 0 0
T40 0 20 0 0
T45 0 5 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 367212259 605314 0 0
T3 2187 1 0 0
T4 286543 0 0 0
T5 69538 2118 0 0
T6 42723 2177 0 0
T7 0 6 0 0
T11 385811 0 0 0
T12 168520 13 0 0
T16 1132 0 0 0
T17 2668 2 0 0
T18 846 0 0 0
T19 2178 0 0 0
T26 0 73 0 0
T29 0 1 0 0
T40 0 20 0 0
T45 0 5 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%