Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	370157646	4091	0	0
addr_rd_A	370157646	1715	0	0
bank0_info0_page_cfg_0_rd_A	370157646	2804	0	0
bank0_info0_page_cfg_1_rd_A	370157646	2927	0	0
bank0_info0_page_cfg_2_rd_A	370157646	2855	0	0
bank0_info0_page_cfg_3_rd_A	370157646	2940	0	0
bank0_info0_page_cfg_4_rd_A	370157646	2824	0	0
bank0_info0_page_cfg_5_rd_A	370157646	2831	0	0
bank0_info0_page_cfg_6_rd_A	370157646	3175	0	0
bank0_info0_page_cfg_7_rd_A	370157646	3060	0	0
bank0_info0_page_cfg_8_rd_A	370157646	2357	0	0
bank0_info0_page_cfg_9_rd_A	370157646	3221	0	0
bank0_info0_regwen_0_rd_A	370157646	1603	0	0
bank0_info0_regwen_1_rd_A	370157646	2289	0	0
bank0_info0_regwen_2_rd_A	370157646	2156	0	0
bank0_info0_regwen_3_rd_A	370157646	1680	0	0
bank0_info0_regwen_4_rd_A	370157646	1592	0	0
bank0_info0_regwen_5_rd_A	370157646	1702	0	0
bank0_info0_regwen_6_rd_A	370157646	2083	0	0
bank0_info0_regwen_7_rd_A	370157646	1729	0	0
bank0_info0_regwen_8_rd_A	370157646	2104	0	0
bank0_info0_regwen_9_rd_A	370157646	1700	0	0
bank0_info1_page_cfg_rd_A	370157646	2937	0	0
bank0_info1_regwen_rd_A	370157646	2039	0	0
bank0_info2_page_cfg_0_rd_A	370157646	2466	0	0
bank0_info2_page_cfg_1_rd_A	370157646	2949	0	0
bank0_info2_regwen_0_rd_A	370157646	1729	0	0
bank0_info2_regwen_1_rd_A	370157646	2123	0	0
bank1_info0_page_cfg_0_rd_A	370157646	3079	0	0
bank1_info0_page_cfg_1_rd_A	370157646	2572	0	0
bank1_info0_page_cfg_2_rd_A	370157646	3018	0	0
bank1_info0_page_cfg_3_rd_A	370157646	3057	0	0
bank1_info0_page_cfg_4_rd_A	370157646	2624	0	0
bank1_info0_page_cfg_5_rd_A	370157646	2387	0	0
bank1_info0_page_cfg_6_rd_A	370157646	2792	0	0
bank1_info0_page_cfg_7_rd_A	370157646	2908	0	0
bank1_info0_page_cfg_8_rd_A	370157646	2978	0	0
bank1_info0_page_cfg_9_rd_A	370157646	3232	0	0
bank1_info0_regwen_0_rd_A	370157646	1772	0	0
bank1_info0_regwen_1_rd_A	370157646	2072	0	0
bank1_info0_regwen_2_rd_A	370157646	1686	0	0
bank1_info0_regwen_3_rd_A	370157646	2053	0	0
bank1_info0_regwen_4_rd_A	370157646	2191	0	0
bank1_info0_regwen_5_rd_A	370157646	1994	0	0
bank1_info0_regwen_6_rd_A	370157646	2087	0	0
bank1_info0_regwen_7_rd_A	370157646	2285	0	0
bank1_info0_regwen_8_rd_A	370157646	2275	0	0
bank1_info0_regwen_9_rd_A	370157646	1699	0	0
bank1_info1_page_cfg_rd_A	370157646	2970	0	0
bank1_info1_regwen_rd_A	370157646	2143	0	0
bank1_info2_page_cfg_0_rd_A	370157646	3041	0	0
bank1_info2_page_cfg_1_rd_A	370157646	3304	0	0
bank1_info2_regwen_0_rd_A	370157646	2268	0	0
bank1_info2_regwen_1_rd_A	370157646	2197	0	0
bank_cfg_regwen_rd_A	370157646	2109	0	0
default_region_rd_A	370157646	3045	0	0
exec_rd_A	370157646	2136	0	0
fifo_lvl_rd_A	370157646	1954	0	0
fifo_rst_rd_A	370157646	2080	0	0
hw_info_cfg_override_rd_A	370157646	2276	0	0
intr_enable_rd_A	370157646	2317	0	0
mp_region_0_rd_A	370157646	2271	0	0
mp_region_1_rd_A	370157646	2323	0	0
mp_region_2_rd_A	370157646	2319	0	0
mp_region_3_rd_A	370157646	2285	0	0
mp_region_4_rd_A	370157646	2263	0	0
mp_region_5_rd_A	370157646	2170	0	0
mp_region_6_rd_A	370157646	2228	0	0
mp_region_7_rd_A	370157646	2386	0	0
mp_region_cfg_0_rd_A	370157646	3036	0	0
mp_region_cfg_1_rd_A	370157646	3002	0	0
mp_region_cfg_2_rd_A	370157646	3074	0	0
mp_region_cfg_3_rd_A	370157646	3063	0	0
mp_region_cfg_4_rd_A	370157646	3092	0	0
mp_region_cfg_5_rd_A	370157646	2853	0	0
mp_region_cfg_6_rd_A	370157646	3046	0	0
mp_region_cfg_7_rd_A	370157646	3072	0	0
phy_alert_cfg_rd_A	370157646	677	0	0
region_cfg_regwen_0_rd_A	370157646	2122	0	0
region_cfg_regwen_1_rd_A	370157646	1685	0	0
region_cfg_regwen_2_rd_A	370157646	2113	0	0
region_cfg_regwen_3_rd_A	370157646	2173	0	0
region_cfg_regwen_4_rd_A	370157646	2193	0	0
region_cfg_regwen_5_rd_A	370157646	1665	0	0
region_cfg_regwen_6_rd_A	370157646	2223	0	0
region_cfg_regwen_7_rd_A	370157646	2156	0	0
scratch_rd_A	370157646	2126	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	4091	0	0
T111	3610	25	0	0
T112	8945	1	0	0
T113	3787	12	0	0
T114	2836	23	0	0
T206	71309	4	0	0
T207	3247	137	0	0
T209	32954	1	0	0
T210	5924	359	0	0
T223	3741	149	0	0
T224	5476	1	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1715	0	0
T112	8945	15	0	0
T224	5476	10	0	0
T244	9918	38	0	0
T272	5041	10	0	0
T299	2768	2	0	0
T300	20561	43	0	0
T301	6085	12	0	0
T302	9909	17	0	0
T303	6421	6	0	0
T304	10521	12	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2804	0	0
T112	8945	14	0	0
T224	5476	25	0	0
T244	9918	25	0	0
T272	5041	3	0	0
T300	20561	75	0	0
T301	6085	11	0	0
T302	9909	6	0	0
T303	6421	34	0	0
T304	10521	24	0	0
T305	328371	374	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2927	0	0
T112	8945	38	0	0
T224	5476	12	0	0
T244	9918	10	0	0
T272	5041	2	0	0
T299	2768	2	0	0
T300	20561	7	0	0
T301	6085	11	0	0
T302	9909	10	0	0
T303	6421	42	0	0
T304	10521	25	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2855	0	0
T112	8945	5	0	0
T224	5476	8	0	0
T244	9918	5	0	0
T272	5041	17	0	0
T300	20561	21	0	0
T301	6085	7	0	0
T302	9909	3	0	0
T303	6421	23	0	0
T304	10521	16	0	0
T305	328371	469	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2940	0	0
T112	8945	14	0	0
T224	5476	31	0	0
T244	9918	5	0	0
T272	5041	7	0	0
T299	2768	9	0	0
T300	20561	10	0	0
T301	6085	3	0	0
T302	9909	8	0	0
T303	6421	12	0	0
T304	10521	38	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2824	0	0
T112	8945	9	0	0
T224	5476	5	0	0
T244	9918	18	0	0
T272	5041	38	0	0
T299	2768	9	0	0
T300	20561	49	0	0
T302	9909	12	0	0
T304	10521	35	0	0
T305	328371	456	0	0
T306	319880	473	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2831	0	0
T112	8945	13	0	0
T224	5476	20	0	0
T244	9918	17	0	0
T272	5041	9	0	0
T299	2768	4	0	0
T300	20561	81	0	0
T301	6085	4	0	0
T303	6421	3	0	0
T304	10521	34	0	0
T305	328371	433	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3175	0	0
T112	8945	19	0	0
T224	5476	40	0	0
T244	9918	34	0	0
T272	5041	29	0	0
T299	2768	7	0	0
T300	20561	49	0	0
T301	6085	19	0	0
T302	9909	9	0	0
T303	6421	12	0	0
T304	10521	40	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3060	0	0
T112	8945	12	0	0
T224	5476	9	0	0
T244	9918	7	0	0
T272	5041	6	0	0
T299	2768	6	0	0
T300	20561	47	0	0
T301	6085	24	0	0
T302	9909	13	0	0
T303	6421	19	0	0
T304	10521	65	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2357	0	0
T112	8945	7	0	0
T224	5476	8	0	0
T272	5041	10	0	0
T299	2768	5	0	0
T300	20561	33	0	0
T301	6085	23	0	0
T302	9909	5	0	0
T303	6421	8	0	0
T304	10521	38	0	0
T305	328371	456	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3221	0	0
T112	8945	39	0	0
T224	5476	33	0	0
T244	9918	22	0	0
T272	5041	23	0	0
T299	2768	2	0	0
T300	20561	11	0	0
T301	6085	10	0	0
T302	9909	1	0	0
T303	6421	18	0	0
T304	10521	48	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1603	0	0
T112	8945	2	0	0
T224	5476	7	0	0
T244	9918	2	0	0
T272	5041	14	0	0
T299	2768	2	0	0
T300	20561	72	0	0
T301	6085	5	0	0
T302	9909	7	0	0
T303	6421	7	0	0
T304	10521	13	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2289	0	0
T112	8945	5	0	0
T224	5476	5	0	0
T272	5041	10	0	0
T300	20561	79	0	0
T302	9909	12	0	0
T303	6421	5	0	0
T304	10521	6	0	0
T305	328371	447	0	0
T306	319880	414	0	0
T307	3345	4	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2156	0	0
T112	8945	11	0	0
T224	5476	7	0	0
T272	5041	7	0	0
T299	2768	4	0	0
T300	20561	35	0	0
T302	9909	13	0	0
T304	10521	32	0	0
T305	328371	480	0	0
T306	319880	466	0	0
T307	3345	5	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1680	0	0
T112	8945	3	0	0
T224	5476	13	0	0
T244	9918	8	0	0
T272	5041	8	0	0
T299	2768	7	0	0
T300	20561	66	0	0
T301	6085	7	0	0
T302	9909	14	0	0
T304	10521	12	0	0
T305	328371	485	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1592	0	0
T112	8945	1	0	0
T224	5476	8	0	0
T244	9918	16	0	0
T272	5041	9	0	0
T299	2768	5	0	0
T300	20561	31	0	0
T301	6085	2	0	0
T302	9909	4	0	0
T304	10521	4	0	0
T305	328371	419	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1702	0	0
T112	8945	13	0	0
T224	5476	17	0	0
T244	9918	18	0	0
T272	5041	13	0	0
T299	2768	1	0	0
T300	20561	18	0	0
T301	6085	8	0	0
T302	9909	19	0	0
T303	6421	3	0	0
T304	10521	13	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2083	0	0
T112	8945	13	0	0
T224	5476	14	0	0
T244	9918	33	0	0
T272	5041	13	0	0
T299	2768	5	0	0
T300	20561	34	0	0
T302	9909	15	0	0
T303	6421	14	0	0
T304	10521	19	0	0
T305	328371	445	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1729	0	0
T112	8945	9	0	0
T224	5476	7	0	0
T244	9918	25	0	0
T272	5041	14	0	0
T299	2768	8	0	0
T300	20561	56	0	0
T302	9909	21	0	0
T303	6421	5	0	0
T304	10521	17	0	0
T305	328371	407	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2104	0	0
T112	8945	1	0	0
T224	5476	5	0	0
T244	9918	7	0	0
T272	5041	8	0	0
T299	2768	2	0	0
T300	20561	83	0	0
T301	6085	5	0	0
T302	9909	5	0	0
T303	6421	5	0	0
T304	10521	17	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1700	0	0
T112	8945	7	0	0
T224	5476	6	0	0
T244	9918	10	0	0
T272	5041	5	0	0
T299	2768	4	0	0
T300	20561	38	0	0
T302	9909	17	0	0
T304	10521	14	0	0
T305	328371	495	0	0
T306	319880	446	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2937	0	0
T112	8945	15	0	0
T224	5476	29	0	0
T244	9918	53	0	0
T272	5041	5	0	0
T299	2768	8	0	0
T300	20561	55	0	0
T301	6085	41	0	0
T302	9909	4	0	0
T303	6421	12	0	0
T304	10521	55	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2039	0	0
T112	8945	3	0	0
T224	5476	7	0	0
T244	9918	27	0	0
T272	5041	6	0	0
T300	20561	15	0	0
T301	6085	8	0	0
T302	9909	24	0	0
T303	6421	8	0	0
T304	10521	16	0	0
T305	328371	404	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2466	0	0
T112	8945	29	0	0
T224	5476	32	0	0
T244	9918	14	0	0
T272	5041	21	0	0
T299	2768	1	0	0
T300	20561	4	0	0
T301	6085	12	0	0
T302	9909	16	0	0
T303	6421	32	0	0
T304	10521	13	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2949	0	0
T112	8945	12	0	0
T224	5476	5	0	0
T244	9918	1	0	0
T272	5041	17	0	0
T299	2768	6	0	0
T300	20561	18	0	0
T301	6085	24	0	0
T302	9909	6	0	0
T303	6421	11	0	0
T304	10521	5	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1729	0	0
T112	8945	24	0	0
T224	5476	8	0	0
T244	9918	48	0	0
T272	5041	8	0	0
T299	2768	3	0	0
T300	20561	22	0	0
T301	6085	6	0	0
T302	9909	1	0	0
T303	6421	3	0	0
T304	10521	11	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2123	0	0
T112	8945	14	0	0
T224	5476	4	0	0
T244	9918	6	0	0
T272	5041	7	0	0
T299	2768	2	0	0
T300	20561	39	0	0
T301	6085	4	0	0
T302	9909	23	0	0
T304	10521	23	0	0
T305	328371	444	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3079	0	0
T112	8945	14	0	0
T224	5476	34	0	0
T244	9918	19	0	0
T272	5041	32	0	0
T299	2768	7	0	0
T300	20561	74	0	0
T301	6085	10	0	0
T302	9909	5	0	0
T303	6421	10	0	0
T304	10521	34	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2572	0	0
T112	8945	12	0	0
T224	5476	15	0	0
T244	9918	22	0	0
T272	5041	15	0	0
T299	2768	1	0	0
T300	20561	24	0	0
T301	6085	30	0	0
T302	9909	11	0	0
T303	6421	29	0	0
T304	10521	30	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3018	0	0
T112	8945	17	0	0
T224	5476	11	0	0
T244	9918	27	0	0
T272	5041	10	0	0
T300	20561	66	0	0
T301	6085	15	0	0
T302	9909	24	0	0
T303	6421	30	0	0
T304	10521	52	0	0
T305	328371	420	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3057	0	0
T112	8945	15	0	0
T224	5476	41	0	0
T244	9918	9	0	0
T272	5041	29	0	0
T299	2768	4	0	0
T300	20561	29	0	0
T301	6085	3	0	0
T302	9909	5	0	0
T303	6421	6	0	0
T304	10521	63	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2624	0	0
T112	8945	12	0	0
T224	5476	26	0	0
T244	9918	41	0	0
T272	5041	5	0	0
T300	20561	77	0	0
T301	6085	37	0	0
T302	9909	29	0	0
T303	6421	42	0	0
T304	10521	32	0	0
T305	328371	420	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2387	0	0
T112	8945	23	0	0
T224	5476	44	0	0
T244	9918	25	0	0
T272	5041	2	0	0
T300	20561	20	0	0
T303	6421	1	0	0
T304	10521	45	0	0
T305	328371	450	0	0
T306	319880	418	0	0
T307	3345	32	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2792	0	0
T112	8945	6	0	0
T224	5476	5	0	0
T244	9918	27	0	0
T272	5041	2	0	0
T299	2768	6	0	0
T300	20561	45	0	0
T301	6085	15	0	0
T302	9909	24	0	0
T303	6421	25	0	0
T304	10521	43	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2908	0	0
T112	8945	21	0	0
T224	5476	8	0	0
T244	9918	44	0	0
T272	5041	9	0	0
T299	2768	2	0	0
T300	20561	34	0	0
T301	6085	6	0	0
T302	9909	19	0	0
T303	6421	38	0	0
T304	10521	59	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2978	0	0
T112	8945	7	0	0
T224	5476	9	0	0
T244	9918	43	0	0
T272	5041	42	0	0
T299	2768	9	0	0
T300	20561	18	0	0
T301	6085	9	0	0
T302	9909	6	0	0
T304	10521	30	0	0
T305	328371	413	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3232	0	0
T112	8945	11	0	0
T224	5476	40	0	0
T244	9918	24	0	0
T272	5041	28	0	0
T299	2768	7	0	0
T300	20561	52	0	0
T301	6085	1	0	0
T302	9909	13	0	0
T303	6421	28	0	0
T304	10521	34	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1772	0	0
T112	8945	15	0	0
T224	5476	7	0	0
T244	9918	13	0	0
T272	5041	11	0	0
T299	2768	8	0	0
T300	20561	33	0	0
T301	6085	6	0	0
T302	9909	30	0	0
T303	6421	1	0	0
T304	10521	24	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2072	0	0
T112	8945	1	0	0
T224	5476	6	0	0
T272	5041	2	0	0
T299	2768	6	0	0
T300	20561	24	0	0
T301	6085	1	0	0
T302	9909	31	0	0
T304	10521	10	0	0
T305	328371	406	0	0
T306	319880	482	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1686	0	0
T112	8945	2	0	0
T224	5476	13	0	0
T244	9918	6	0	0
T272	5041	3	0	0
T299	2768	1	0	0
T300	20561	54	0	0
T301	6085	3	0	0
T302	9909	13	0	0
T303	6421	1	0	0
T304	10521	17	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2053	0	0
T112	8945	9	0	0
T224	5476	4	0	0
T244	9918	19	0	0
T272	5041	4	0	0
T299	2768	2	0	0
T300	20561	17	0	0
T302	9909	15	0	0
T303	6421	1	0	0
T304	10521	9	0	0
T305	328371	487	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2191	0	0
T112	8945	9	0	0
T224	5476	7	0	0
T244	9918	10	0	0
T272	5041	10	0	0
T299	2768	4	0	0
T300	20561	43	0	0
T301	6085	1	0	0
T302	9909	14	0	0
T303	6421	3	0	0
T304	10521	7	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1994	0	0
T112	8945	6	0	0
T224	5476	8	0	0
T244	9918	30	0	0
T272	5041	10	0	0
T299	2768	3	0	0
T300	20561	55	0	0
T301	6085	7	0	0
T302	9909	30	0	0
T303	6421	9	0	0
T304	10521	5	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2087	0	0
T112	8945	9	0	0
T224	5476	1	0	0
T244	9918	16	0	0
T272	5041	6	0	0
T299	2768	4	0	0
T300	20561	50	0	0
T302	9909	4	0	0
T304	10521	7	0	0
T305	328371	450	0	0
T306	319880	447	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2285	0	0
T112	8945	6	0	0
T224	5476	13	0	0
T244	9918	18	0	0
T272	5041	11	0	0
T299	2768	1	0	0
T300	20561	27	0	0
T301	6085	3	0	0
T302	9909	10	0	0
T303	6421	10	0	0
T304	10521	15	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2275	0	0
T112	8945	14	0	0
T224	5476	16	0	0
T244	9918	1	0	0
T272	5041	5	0	0
T299	2768	7	0	0
T300	20561	74	0	0
T301	6085	9	0	0
T302	9909	16	0	0
T303	6421	8	0	0
T304	10521	9	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1699	0	0
T112	8945	5	0	0
T224	5476	15	0	0
T244	9918	35	0	0
T299	2768	5	0	0
T300	20561	42	0	0
T302	9909	6	0	0
T303	6421	13	0	0
T304	10521	17	0	0
T305	328371	401	0	0
T306	319880	501	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2970	0	0
T112	8945	10	0	0
T224	5476	43	0	0
T244	9918	23	0	0
T272	5041	12	0	0
T300	20561	28	0	0
T301	6085	22	0	0
T302	9909	9	0	0
T304	10521	21	0	0
T305	328371	500	0	0
T306	319880	432	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2143	0	0
T112	8945	14	0	0
T224	5476	11	0	0
T244	9918	10	0	0
T272	5041	10	0	0
T299	2768	6	0	0
T300	20561	50	0	0
T301	6085	7	0	0
T302	9909	9	0	0
T303	6421	6	0	0
T304	10521	17	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3041	0	0
T112	8945	33	0	0
T224	5476	39	0	0
T244	9918	30	0	0
T272	5041	23	0	0
T299	2768	1	0	0
T300	20561	66	0	0
T301	6085	20	0	0
T302	9909	27	0	0
T303	6421	9	0	0
T304	10521	76	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3304	0	0
T112	8945	51	0	0
T224	5476	35	0	0
T244	9918	15	0	0
T272	5041	30	0	0
T299	2768	2	0	0
T300	20561	44	0	0
T301	6085	16	0	0
T302	9909	12	0	0
T303	6421	34	0	0
T304	10521	63	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2268	0	0
T112	8945	15	0	0
T224	5476	16	0	0
T244	9918	16	0	0
T272	5041	12	0	0
T299	2768	1	0	0
T300	20561	34	0	0
T301	6085	3	0	0
T302	9909	23	0	0
T303	6421	2	0	0
T304	10521	20	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2197	0	0
T112	8945	13	0	0
T224	5476	3	0	0
T244	9918	3	0	0
T272	5041	10	0	0
T299	2768	7	0	0
T300	20561	38	0	0
T302	9909	6	0	0
T304	10521	16	0	0
T305	328371	430	0	0
T306	319880	474	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2109	0	0
T112	8945	18	0	0
T224	5476	13	0	0
T272	5041	9	0	0
T299	2768	2	0	0
T300	20561	15	0	0
T301	6085	13	0	0
T302	9909	9	0	0
T303	6421	14	0	0
T304	10521	13	0	0
T305	328371	429	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3045	0	0
T112	8945	26	0	0
T224	5476	21	0	0
T244	9918	6	0	0
T272	5041	8	0	0
T299	2768	4	0	0
T300	20561	22	0	0
T301	6085	8	0	0
T302	9909	11	0	0
T303	6421	25	0	0
T304	10521	56	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2136	0	0
T112	8945	7	0	0
T224	5476	9	0	0
T244	9918	8	0	0
T272	5041	6	0	0
T299	2768	5	0	0
T300	20561	51	0	0
T302	9909	6	0	0
T304	10521	26	0	0
T305	328371	472	0	0
T306	319880	436	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1954	0	0
T112	8945	21	0	0
T224	5476	12	0	0
T244	9918	30	0	0
T272	5041	11	0	0
T299	2768	6	0	0
T300	20561	20	0	0
T301	6085	7	0	0
T302	9909	5	0	0
T304	10521	32	0	0
T305	328371	534	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2080	0	0
T224	5476	11	0	0
T244	9918	1	0	0
T272	5041	8	0	0
T299	2768	1	0	0
T300	20561	35	0	0
T301	6085	11	0	0
T302	9909	5	0	0
T303	6421	3	0	0
T304	10521	14	0	0
T305	328371	455	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2276	0	0
T224	5476	12	0	0
T244	9918	40	0	0
T272	5041	9	0	0
T299	2768	5	0	0
T300	20561	34	0	0
T301	6085	8	0	0
T302	9909	3	0	0
T303	6421	8	0	0
T304	10521	15	0	0
T305	328371	452	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2317	0	0
T112	8945	34	0	0
T224	5476	9	0	0
T244	9918	33	0	0
T272	5041	19	0	0
T299	2768	3	0	0
T300	20561	8	0	0
T301	6085	19	0	0
T302	9909	7	0	0
T303	6421	23	0	0
T304	10521	47	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2271	0	0
T112	8945	10	0	0
T224	5476	12	0	0
T244	9918	38	0	0
T272	5041	13	0	0
T299	2768	9	0	0
T300	20561	17	0	0
T302	9909	4	0	0
T304	10521	17	0	0
T305	328371	472	0	0
T306	319880	432	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2323	0	0
T112	8945	21	0	0
T224	5476	15	0	0
T244	9918	7	0	0
T272	5041	4	0	0
T300	20561	78	0	0
T301	6085	5	0	0
T302	9909	4	0	0
T303	6421	1	0	0
T304	10521	15	0	0
T305	328371	477	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2319	0	0
T112	8945	4	0	0
T224	5476	3	0	0
T244	9918	4	0	0
T272	5041	10	0	0
T299	2768	5	0	0
T300	20561	35	0	0
T302	9909	11	0	0
T303	6421	3	0	0
T304	10521	10	0	0
T305	328371	446	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2285	0	0
T112	8945	7	0	0
T224	5476	19	0	0
T244	9918	10	0	0
T272	5041	13	0	0
T299	2768	1	0	0
T300	20561	38	0	0
T301	6085	8	0	0
T302	9909	12	0	0
T304	10521	25	0	0
T305	328371	443	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2263	0	0
T112	8945	4	0	0
T224	5476	7	0	0
T272	5041	2	0	0
T299	2768	9	0	0
T300	20561	62	0	0
T301	6085	5	0	0
T302	9909	17	0	0
T303	6421	2	0	0
T304	10521	22	0	0
T305	328371	439	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2170	0	0
T112	8945	9	0	0
T224	5476	14	0	0
T244	9918	35	0	0
T272	5041	8	0	0
T299	2768	7	0	0
T300	20561	20	0	0
T304	10521	13	0	0
T305	328371	445	0	0
T306	319880	397	0	0
T307	3345	10	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2228	0	0
T112	8945	14	0	0
T224	5476	9	0	0
T244	9918	28	0	0
T272	5041	2	0	0
T299	2768	9	0	0
T300	20561	58	0	0
T303	6421	8	0	0
T304	10521	11	0	0
T305	328371	455	0	0
T306	319880	406	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2386	0	0
T112	8945	9	0	0
T224	5476	23	0	0
T244	9918	53	0	0
T272	5041	6	0	0
T299	2768	5	0	0
T300	20561	62	0	0
T301	6085	15	0	0
T302	9909	10	0	0
T303	6421	8	0	0
T304	10521	39	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3036	0	0
T112	8945	4	0	0
T224	5476	20	0	0
T244	9918	28	0	0
T272	5041	18	0	0
T299	2768	1	0	0
T300	20561	54	0	0
T301	6085	34	0	0
T303	6421	32	0	0
T304	10521	64	0	0
T305	328371	455	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3002	0	0
T112	8945	21	0	0
T224	5476	13	0	0
T244	9918	4	0	0
T272	5041	32	0	0
T299	2768	7	0	0
T300	20561	30	0	0
T301	6085	8	0	0
T302	9909	4	0	0
T303	6421	14	0	0
T304	10521	50	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3074	0	0
T112	8945	3	0	0
T224	5476	39	0	0
T244	9918	19	0	0
T272	5041	13	0	0
T299	2768	3	0	0
T300	20561	33	0	0
T301	6085	21	0	0
T302	9909	13	0	0
T303	6421	25	0	0
T304	10521	38	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3063	0	0
T112	8945	23	0	0
T224	5476	11	0	0
T244	9918	23	0	0
T272	5041	30	0	0
T299	2768	7	0	0
T300	20561	29	0	0
T301	6085	6	0	0
T302	9909	10	0	0
T303	6421	12	0	0
T304	10521	58	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3092	0	0
T112	8945	7	0	0
T224	5476	9	0	0
T244	9918	23	0	0
T272	5041	27	0	0
T299	2768	1	0	0
T300	20561	66	0	0
T301	6085	7	0	0
T302	9909	29	0	0
T303	6421	4	0	0
T304	10521	64	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2853	0	0
T112	8945	15	0	0
T224	5476	11	0	0
T244	9918	33	0	0
T272	5041	6	0	0
T299	2768	3	0	0
T300	20561	31	0	0
T301	6085	41	0	0
T303	6421	7	0	0
T304	10521	41	0	0
T305	328371	431	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3046	0	0
T112	8945	4	0	0
T224	5476	25	0	0
T244	9918	38	0	0
T272	5041	5	0	0
T300	20561	40	0	0
T301	6085	28	0	0
T302	9909	15	0	0
T303	6421	15	0	0
T304	10521	16	0	0
T305	328371	437	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	3072	0	0
T112	8945	22	0	0
T224	5476	4	0	0
T244	9918	45	0	0
T272	5041	6	0	0
T299	2768	1	0	0
T300	20561	71	0	0
T301	6085	2	0	0
T302	9909	21	0	0
T303	6421	12	0	0
T304	10521	41	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	677	0	0
T112	8945	1	0	0
T224	5476	3	0	0
T244	9918	23	0	0
T272	5041	3	0	0
T299	2768	2	0	0
T300	20561	31	0	0
T302	9909	21	0	0
T304	10521	14	0	0
T308	19706	12	0	0
T309	9408	10	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2122	0	0
T112	8945	9	0	0
T224	5476	3	0	0
T244	9918	55	0	0
T272	5041	1	0	0
T299	2768	8	0	0
T300	20561	29	0	0
T301	6085	9	0	0
T302	9909	6	0	0
T303	6421	3	0	0
T304	10521	6	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1685	0	0
T112	8945	5	0	0
T224	5476	8	0	0
T244	9918	13	0	0
T299	2768	5	0	0
T300	20561	55	0	0
T301	6085	5	0	0
T302	9909	12	0	0
T303	6421	6	0	0
T304	10521	16	0	0
T305	328371	431	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2113	0	0
T224	5476	12	0	0
T244	9918	35	0	0
T272	5041	12	0	0
T299	2768	4	0	0
T300	20561	45	0	0
T301	6085	5	0	0
T304	10521	20	0	0
T305	328371	412	0	0
T306	319880	491	0	0
T307	3345	3	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2173	0	0
T112	8945	15	0	0
T224	5476	10	0	0
T272	5041	3	0	0
T299	2768	2	0	0
T300	20561	18	0	0
T301	6085	3	0	0
T302	9909	17	0	0
T304	10521	14	0	0
T305	328371	473	0	0
T306	319880	478	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2193	0	0
T112	8945	9	0	0
T224	5476	8	0	0
T244	9918	20	0	0
T272	5041	2	0	0
T299	2768	4	0	0
T300	20561	38	0	0
T301	6085	7	0	0
T302	9909	7	0	0
T304	10521	18	0	0
T305	328371	486	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	1665	0	0
T112	8945	6	0	0
T224	5476	11	0	0
T244	9918	50	0	0
T272	5041	18	0	0
T299	2768	2	0	0
T300	20561	30	0	0
T301	6085	5	0	0
T302	9909	12	0	0
T304	10521	12	0	0
T305	328371	442	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2223	0	0
T112	8945	6	0	0
T224	5476	6	0	0
T244	9918	32	0	0
T272	5041	17	0	0
T299	2768	3	0	0
T300	20561	30	0	0
T301	6085	4	0	0
T302	9909	3	0	0
T304	10521	17	0	0
T305	328371	421	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2156	0	0
T112	8945	14	0	0
T224	5476	12	0	0
T244	9918	54	0	0
T272	5041	8	0	0
T299	2768	6	0	0
T300	20561	47	0	0
T302	9909	43	0	0
T303	6421	7	0	0
T304	10521	16	0	0
T305	328371	429	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370157646	2126	0	0
T112	8945	8	0	0
T224	5476	4	0	0
T244	9918	26	0	0
T272	5041	1	0	0
T299	2768	2	0	0
T300	20561	53	0	0
T301	6085	1	0	0
T302	9909	14	0	0
T303	6421	4	0	0
T304	10521	7	0	0