Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18530	1		T71	102		T72	258		T99	40
full_word	4189993	1		T5	16832		T6	16031		T26	16422

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4208247	1		T5	16832		T6	16031		T26	16422
auto[TlIntgErrCmd]	93	1		T212	8		T245	10		T259	3
auto[TlIntgErrData]	97	1		T212	5		T245	5		T259	4
auto[TlIntgErrBoth]	86	1		T212	6		T245	4		T259	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4183726	1		T5	16832		T6	16031		T26	16422
auto[1]	24797	1		T71	162		T72	343		T99	64

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1105	1		T71	7		T72	13		T99	3
auto[TlIntgErrNone]	partial	auto[1]	17178	1		T71	95		T72	245		T99	37
auto[TlIntgErrNone]	full_word	auto[0]	4182508	1		T5	16832		T6	16031		T26	16422
auto[TlIntgErrNone]	full_word	auto[1]	7456	1		T71	67		T72	98		T99	27
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T212	1		T245	5		T259	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T212	7		T245	3		T259	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T245	2		T356	1		T282	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T212	2		T245	3		T259	3
auto[TlIntgErrData]	partial	auto[1]	40	1		T212	2		T245	2		T259	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T212	1		T354	1		T356	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T278	1		T281	1		T354	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T212	4		T245	1		T278	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T212	2		T245	3		T259	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T278	1		T281	1		T356	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1		T259	1		T278	1		T353	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	28601315	1		T1	19685		T2	5948		T3	64
full_word	7834788	1		T1	935		T2	12566		T3	187

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36435803	1		T1	20620		T2	18514		T3	251
auto[TlIntgErrCmd]	91	1		T212	7		T245	6		T259	2
auto[TlIntgErrData]	81	1		T212	5		T245	6		T259	5
auto[TlIntgErrBoth]	128	1		T212	8		T245	8		T259	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31841350	1		T1	19912		T2	9947		T3	123
auto[1]	4594753	1		T1	708		T2	8567		T3	128

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	27865576	1		T1	19616		T2	5621		T3	50
auto[TlIntgErrNone]	partial	auto[1]	735463	1		T1	69		T2	327		T3	14
auto[TlIntgErrNone]	full_word	auto[0]	3975631	1		T1	296		T2	4326		T3	73
auto[TlIntgErrNone]	full_word	auto[1]	3859133	1		T1	639		T2	8240		T3	114
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T212	1		T245	2		T259	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1		T212	5		T245	4		T259	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T278	2		T357	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T212	1		T354	1		T357	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T212	3		T245	4		T259	2
auto[TlIntgErrData]	partial	auto[1]	29	1		T212	1		T245	2		T259	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T275	1		T284	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1		T212	1		T259	1		T281	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1		T212	4		T245	3		T259	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1		T212	4		T245	5		T259	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T313	1		T284	1		T358	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T354	2		T359	1		T355	1