Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1567899552	1564386412	0	0
CheckNGreaterZero_A	4184	4184	0	0
GntImpliesReady_A	1567899552	416396190	0	0
GntImpliesValid_A	1567899552	416396190	0	0
GrantKnown_A	1567899552	1564386412	0	0
IdxKnown_A	1567899552	1564386412	0	0
IndexIsCorrect_A	1567899552	416396190	0	0
NoReadyValidNoGrant_A	1567899552	174613066	0	0
Priority_A	1567899552	440943348	0	0
ReadyAndValidImplyGrant_A	1567899552	416396190	0	0
ReqAndReadyImplyGrant_A	1567899552	416396190	0	0
ReqImpliesValid_A	1567899552	440943348	0	0
ValidKnown_A	1567899552	1564386412	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	1564386412	0	0
T1	586744	586376	0	0
T2	690520	690160	0	0
T3	15472	15252	0	0
T4	1760	1552	0	0
T10	3376568	3376472	0	0
T11	5884	5112	0	0
T12	16652	14004	0	0
T15	780684	780392	0	0
T16	1541040	1540992	0	0
T17	3608	3372	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4184	4184	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	416396190	0	0
T1	586744	275944	0	0
T2	690520	30730	0	0
T3	15472	934	0	0
T4	1760	64	0	0
T5	0	20536	0	0
T6	0	16022	0	0
T10	3376568	1088160	0	0
T11	5884	134	0	0
T12	16652	450	0	0
T15	780684	345658	0	0
T16	1541040	514598	0	0
T17	3608	64	0	0
T26	0	38856	0	0
T38	0	21178	0	0
T56	0	269612	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	416396190	0	0
T1	586744	275944	0	0
T2	690520	30730	0	0
T3	15472	934	0	0
T4	1760	64	0	0
T5	0	20536	0	0
T6	0	16022	0	0
T10	3376568	1088160	0	0
T11	5884	134	0	0
T12	16652	450	0	0
T15	780684	345658	0	0
T16	1541040	514598	0	0
T17	3608	64	0	0
T26	0	38856	0	0
T38	0	21178	0	0
T56	0	269612	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	1564386412	0	0
T1	586744	586376	0	0
T2	690520	690160	0	0
T3	15472	15252	0	0
T4	1760	1552	0	0
T10	3376568	3376472	0	0
T11	5884	5112	0	0
T12	16652	14004	0	0
T15	780684	780392	0	0
T16	1541040	1540992	0	0
T17	3608	3372	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	1564386412	0	0
T1	586744	586376	0	0
T2	690520	690160	0	0
T3	15472	15252	0	0
T4	1760	1552	0	0
T10	3376568	3376472	0	0
T11	5884	5112	0	0
T12	16652	14004	0	0
T15	780684	780392	0	0
T16	1541040	1540992	0	0
T17	3608	3372	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	416396190	0	0
T1	586744	275944	0	0
T2	690520	30730	0	0
T3	15472	934	0	0
T4	1760	64	0	0
T5	0	20536	0	0
T6	0	16022	0	0
T10	3376568	1088160	0	0
T11	5884	134	0	0
T12	16652	450	0	0
T15	780684	345658	0	0
T16	1541040	514598	0	0
T17	3608	64	0	0
T26	0	38856	0	0
T38	0	21178	0	0
T56	0	269612	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	174613066	0	0
T1	586744	1092	0	0
T2	690520	4224	0	0
T3	15472	468	0	0
T4	1760	256	0	0
T5	0	25010	0	0
T6	0	525994	0	0
T10	3376568	425034	0	0
T11	5884	536	0	0
T12	16652	1600	0	0
T15	780684	256	0	0
T16	1541040	2109952	0	0
T17	3608	256	0	0
T19	0	6974	0	0
T26	0	1191730	0	0
T38	0	62342	0	0
T56	0	1051648	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	440943348	0	0
T1	586744	275944	0	0
T2	690520	30730	0	0
T3	15472	934	0	0
T4	1760	64	0	0
T5	0	26808	0	0
T6	0	298722	0	0
T10	3376568	1088160	0	0
T11	5884	134	0	0
T12	16652	450	0	0
T15	780684	345658	0	0
T16	1541040	514598	0	0
T17	3608	64	0	0
T26	0	299042	0	0
T38	0	22984	0	0
T56	0	269612	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	416396190	0	0
T1	586744	275944	0	0
T2	690520	30730	0	0
T3	15472	934	0	0
T4	1760	64	0	0
T5	0	20536	0	0
T6	0	16022	0	0
T10	3376568	1088160	0	0
T11	5884	134	0	0
T12	16652	450	0	0
T15	780684	345658	0	0
T16	1541040	514598	0	0
T17	3608	64	0	0
T26	0	38856	0	0
T38	0	21178	0	0
T56	0	269612	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	416396190	0	0
T1	586744	275944	0	0
T2	690520	30730	0	0
T3	15472	934	0	0
T4	1760	64	0	0
T5	0	20536	0	0
T6	0	16022	0	0
T10	3376568	1088160	0	0
T11	5884	134	0	0
T12	16652	450	0	0
T15	780684	345658	0	0
T16	1541040	514598	0	0
T17	3608	64	0	0
T26	0	38856	0	0
T38	0	21178	0	0
T56	0	269612	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	440943348	0	0
T1	586744	275944	0	0
T2	690520	30730	0	0
T3	15472	934	0	0
T4	1760	64	0	0
T5	0	26808	0	0
T6	0	298722	0	0
T10	3376568	1088160	0	0
T11	5884	134	0	0
T12	16652	450	0	0
T15	780684	345658	0	0
T16	1541040	514598	0	0
T17	3608	64	0	0
T26	0	299042	0	0
T38	0	22984	0	0
T56	0	269612	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567899552	1564386412	0	0
T1	586744	586376	0	0
T2	690520	690160	0	0
T3	15472	15252	0	0
T4	1760	1552	0	0
T10	3376568	3376472	0	0
T11	5884	5112	0	0
T12	16652	14004	0	0
T15	780684	780392	0	0
T16	1541040	1540992	0	0
T17	3608	3372	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391974888	391096603	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	391974888	111092035	0	0
GntImpliesValid_A	391974888	111092035	0	0
GrantKnown_A	391974888	391096603	0	0
IdxKnown_A	391974888	391096603	0	0
IndexIsCorrect_A	391974888	111092035	0	0
NoReadyValidNoGrant_A	391974888	45572011	0	0
Priority_A	391974888	117235104	0	0
ReadyAndValidImplyGrant_A	391974888	111092035	0	0
ReqAndReadyImplyGrant_A	391974888	111092035	0	0
ReqImpliesValid_A	391974888	117235104	0	0
ValidKnown_A	391974888	391096603	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	111092035	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	111092035	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	111092035	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	45572011	0	0
T1	146686	322	0	0
T2	172630	2112	0	0
T3	3868	181	0	0
T4	440	128	0	0
T10	844142	107353	0	0
T11	1471	268	0	0
T12	4163	800	0	0
T15	195171	128	0	0
T16	385260	530688	0	0
T17	902	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	117235104	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	111092035	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	111092035	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	117235104	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391974888	391096603	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	391974888	111091964	0	0
GntImpliesValid_A	391974888	111091964	0	0
GrantKnown_A	391974888	391096603	0	0
IdxKnown_A	391974888	391096603	0	0
IndexIsCorrect_A	391974888	111091964	0	0
NoReadyValidNoGrant_A	391974888	45572013	0	0
Priority_A	391974888	117235031	0	0
ReadyAndValidImplyGrant_A	391974888	111091964	0	0
ReqAndReadyImplyGrant_A	391974888	111091964	0	0
ReqImpliesValid_A	391974888	117235031	0	0
ValidKnown_A	391974888	391096603	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	111091964	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	111091964	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	111091964	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	45572013	0	0
T1	146686	322	0	0
T2	172630	2112	0	0
T3	3868	181	0	0
T4	440	128	0	0
T10	844142	107353	0	0
T11	1471	268	0	0
T12	4163	800	0	0
T15	195171	128	0	0
T16	385260	530688	0	0
T17	902	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	117235031	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	111091964	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	111091964	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	117235031	0	0
T1	146686	2826	0	0
T2	172630	15365	0	0
T3	3868	433	0	0
T4	440	32	0	0
T10	844142	274554	0	0
T11	1471	67	0	0
T12	4163	225	0	0
T15	195171	70999	0	0
T16	385260	129402	0	0
T17	902	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T10
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T10
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T10

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T10

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391974888	391096603	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	391974888	97106126	0	0
GntImpliesValid_A	391974888	97106126	0	0
GrantKnown_A	391974888	391096603	0	0
IdxKnown_A	391974888	391096603	0	0
IndexIsCorrect_A	391974888	97106126	0	0
NoReadyValidNoGrant_A	391974888	41734546	0	0
Priority_A	391974888	103236612	0	0
ReadyAndValidImplyGrant_A	391974888	97106126	0	0
ReqAndReadyImplyGrant_A	391974888	97106126	0	0
ReqImpliesValid_A	391974888	103236612	0	0
ValidKnown_A	391974888	391096603	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	97106126	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	10268	0	0
T6	0	8011	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	19428	0	0
T38	0	10589	0	0
T56	0	134806	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	97106126	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	10268	0	0
T6	0	8011	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	19428	0	0
T38	0	10589	0	0
T56	0	134806	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	97106126	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	10268	0	0
T6	0	8011	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	19428	0	0
T38	0	10589	0	0
T56	0	134806	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	41734546	0	0
T1	146686	224	0	0
T2	172630	0	0	0
T3	3868	53	0	0
T4	440	0	0	0
T5	0	12505	0	0
T6	0	262997	0	0
T10	844142	105164	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	0	0	0
T16	385260	524288	0	0
T17	902	0	0	0
T19	0	3487	0	0
T26	0	595865	0	0
T38	0	31171	0	0
T56	0	525824	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	103236612	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	13404	0	0
T6	0	149361	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	149521	0	0
T38	0	11492	0	0
T56	0	134806	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	97106126	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	10268	0	0
T6	0	8011	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	19428	0	0
T38	0	10589	0	0
T56	0	134806	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	97106126	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	10268	0	0
T6	0	8011	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	19428	0	0
T38	0	10589	0	0
T56	0	134806	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	103236612	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	13404	0	0
T6	0	149361	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	149521	0	0
T38	0	11492	0	0
T56	0	134806	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T10
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T10
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T10

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T3,T10

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391974888	391096603	0	0
CheckNGreaterZero_A	1046	1046	0	0
GntImpliesReady_A	391974888	97106065	0	0
GntImpliesValid_A	391974888	97106065	0	0
GrantKnown_A	391974888	391096603	0	0
IdxKnown_A	391974888	391096603	0	0
IndexIsCorrect_A	391974888	97106065	0	0
NoReadyValidNoGrant_A	391974888	41734496	0	0
Priority_A	391974888	103236601	0	0
ReadyAndValidImplyGrant_A	391974888	97106065	0	0
ReqAndReadyImplyGrant_A	391974888	97106065	0	0
ReqImpliesValid_A	391974888	103236601	0	0
ValidKnown_A	391974888	391096603	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1046	1046	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	97106065	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	10268	0	0
T6	0	8011	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	19428	0	0
T38	0	10589	0	0
T56	0	134806	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	97106065	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	10268	0	0
T6	0	8011	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	19428	0	0
T38	0	10589	0	0
T56	0	134806	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	97106065	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	10268	0	0
T6	0	8011	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	19428	0	0
T38	0	10589	0	0
T56	0	134806	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	41734496	0	0
T1	146686	224	0	0
T2	172630	0	0	0
T3	3868	53	0	0
T4	440	0	0	0
T5	0	12505	0	0
T6	0	262997	0	0
T10	844142	105164	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	0	0	0
T16	385260	524288	0	0
T17	902	0	0	0
T19	0	3487	0	0
T26	0	595865	0	0
T38	0	31171	0	0
T56	0	525824	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	103236601	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	13404	0	0
T6	0	149361	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	149521	0	0
T38	0	11492	0	0
T56	0	134806	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	97106065	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	10268	0	0
T6	0	8011	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	19428	0	0
T38	0	10589	0	0
T56	0	134806	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	97106065	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	10268	0	0
T6	0	8011	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	19428	0	0
T38	0	10589	0	0
T56	0	134806	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	103236601	0	0
T1	146686	135146	0	0
T2	172630	0	0	0
T3	3868	34	0	0
T4	440	0	0	0
T5	0	13404	0	0
T6	0	149361	0	0
T10	844142	269526	0	0
T11	1471	0	0	0
T12	4163	0	0	0
T15	195171	101830	0	0
T16	385260	127897	0	0
T17	902	0	0	0
T26	0	149521	0	0
T38	0	11492	0	0
T56	0	134806	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391974888	391096603	0	0
T1	146686	146594	0	0
T2	172630	172540	0	0
T3	3868	3813	0	0
T4	440	388	0	0
T10	844142	844118	0	0
T11	1471	1278	0	0
T12	4163	3501	0	0
T15	195171	195098	0	0
T16	385260	385248	0	0
T17	902	843	0	0