Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25944291	1		T1	68		T2	188003		T3	17
full_word	7671761	1		T1	45		T2	27890		T4	11900

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33615702	1		T1	113		T2	215893		T3	17
auto[TlIntgErrCmd]	113	1		T63	2		T64	5		T216	8
auto[TlIntgErrData]	115	1		T63	4		T64	3		T216	5
auto[TlIntgErrBoth]	122	1		T63	4		T64	2		T216	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29164238	1		T1	58		T2	194083		T3	16
auto[1]	4451814	1		T1	55		T2	21810		T3	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25216727	1		T1	57		T2	185234		T3	16
auto[TlIntgErrNone]	partial	auto[1]	727257	1		T1	11		T2	2769		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	3947365	1		T1	1		T2	8849		T4	8881
auto[TlIntgErrNone]	full_word	auto[1]	3724353	1		T1	44		T2	19041		T4	3019
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T63	1		T64	3		T216	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1		T63	1		T64	1		T216	5
auto[TlIntgErrCmd]	full_word	auto[0]	9	1		T216	1		T234	1		T272	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T64	1		T234	2		T364	1
auto[TlIntgErrData]	partial	auto[0]	48	1		T63	1		T64	3		T216	2
auto[TlIntgErrData]	partial	auto[1]	49	1		T63	3		T216	3		T233	3
auto[TlIntgErrData]	full_word	auto[0]	9	1		T233	1		T234	1		T364	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T272	1		T337	1		T274	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T63	1		T64	1		T216	4
auto[TlIntgErrBoth]	partial	auto[1]	70	1		T63	3		T64	1		T216	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T233	1		T337	1		T362	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T364	1		T274	1		T366	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20551	1		T99	382		T100	699		T63	9
full_word	4046275	1		T2	41289		T4	16342		T6	16504

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4066491	1		T2	41289		T4	16342		T6	16504
auto[TlIntgErrCmd]	93	1		T63	3		T64	4		T216	6
auto[TlIntgErrData]	130	1		T63	2		T64	3		T216	9
auto[TlIntgErrBoth]	112	1		T63	5		T64	3		T216	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4040896	1		T2	41289		T4	16342		T6	16504
auto[1]	25930	1		T99	528		T100	727		T63	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1563	1		T99	40		T100	68		T215	8
auto[TlIntgErrNone]	partial	auto[1]	18684	1		T99	342		T100	631		T215	383
auto[TlIntgErrNone]	full_word	auto[0]	4039191	1		T2	41289		T4	16342		T6	16504
auto[TlIntgErrNone]	full_word	auto[1]	7053	1		T99	186		T100	96		T215	164
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T63	1		T216	2		T233	4
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T63	2		T64	4		T216	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T367	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T364	1		T275	1		T363	1
auto[TlIntgErrData]	partial	auto[0]	58	1		T63	2		T64	1		T216	1
auto[TlIntgErrData]	partial	auto[1]	54	1		T64	1		T216	7		T233	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T275	1		T362	2		T368	3
auto[TlIntgErrData]	full_word	auto[1]	12	1		T64	1		T216	1		T364	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T63	2		T64	1		T216	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1		T63	2		T64	1		T216	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T64	1		T234	1		T366	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T63	1		T362	1		T368	1