Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1459170744	1455785392	0	0
CheckNGreaterZero_A	4176	4176	0	0
GntImpliesReady_A	1459170744	389733124	0	0
GntImpliesValid_A	1459170744	389733124	0	0
GrantKnown_A	1459170744	1455785392	0	0
IdxKnown_A	1459170744	1455785392	0	0
IndexIsCorrect_A	1459170744	389733124	0	0
NoReadyValidNoGrant_A	1459170744	174013840	0	0
Priority_A	1459170744	413491688	0	0
ReadyAndValidImplyGrant_A	1459170744	389733124	0	0
ReqAndReadyImplyGrant_A	1459170744	389733124	0	0
ReqImpliesValid_A	1459170744	413491688	0	0
ValidKnown_A	1459170744	1455785392	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	1455785392	0	0
T1	5612	5344	0	0
T2	1758696	1758412	0	0
T3	5324	4940	0	0
T4	309908	309572	0	0
T5	852140	851936	0	0
T6	198132	197900	0	0
T10	3576	3372	0	0
T11	15836	13036	0	0
T12	1571448	1571388	0	0
T17	9520	9256	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4176	4176	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	389733124	0	0
T1	2806	64	0	0
T2	1758696	584272	0	0
T3	5324	64	0	0
T4	309908	48114	0	0
T5	852140	366128	0	0
T6	198132	42582	0	0
T10	3576	584	0	0
T11	15836	408	0	0
T12	1571448	514598	0	0
T17	9520	514	0	0
T18	1695246	970460	0	0
T34	0	20052	0	0
T38	0	20	0	0
T55	0	236642	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	389733124	0	0
T1	2806	64	0	0
T2	1758696	584272	0	0
T3	5324	64	0	0
T4	309908	48114	0	0
T5	852140	366128	0	0
T6	198132	42582	0	0
T10	3576	584	0	0
T11	15836	408	0	0
T12	1571448	514598	0	0
T17	9520	514	0	0
T18	1695246	970460	0	0
T34	0	20052	0	0
T38	0	20	0	0
T55	0	236642	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	1455785392	0	0
T1	5612	5344	0	0
T2	1758696	1758412	0	0
T3	5324	4940	0	0
T4	309908	309572	0	0
T5	852140	851936	0	0
T6	198132	197900	0	0
T10	3576	3372	0	0
T11	15836	13036	0	0
T12	1571448	1571388	0	0
T17	9520	9256	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	1455785392	0	0
T1	5612	5344	0	0
T2	1758696	1758412	0	0
T3	5324	4940	0	0
T4	309908	309572	0	0
T5	852140	851936	0	0
T6	198132	197900	0	0
T10	3576	3372	0	0
T11	15836	13036	0	0
T12	1571448	1571388	0	0
T17	9520	9256	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	389733124	0	0
T1	2806	64	0	0
T2	1758696	584272	0	0
T3	5324	64	0	0
T4	309908	48114	0	0
T5	852140	366128	0	0
T6	198132	42582	0	0
T10	3576	584	0	0
T11	15836	408	0	0
T12	1571448	514598	0	0
T17	9520	514	0	0
T18	1695246	970460	0	0
T34	0	20052	0	0
T38	0	20	0	0
T55	0	236642	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	174013840	0	0
T1	2806	256	0	0
T2	1758696	199278	0	0
T3	5324	256	0	0
T4	309908	139108	0	0
T5	852140	256	0	0
T6	198132	54292	0	0
T10	3576	256	0	0
T11	15836	1536	0	0
T12	1571448	2109952	0	0
T17	9520	282	0	0
T18	1695246	8128	0	0
T21	0	50	0	0
T34	0	60190	0	0
T38	0	50	0	0
T55	0	74604	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	413491688	0	0
T1	2806	64	0	0
T2	1758696	716452	0	0
T3	5324	64	0	0
T4	309908	51160	0	0
T5	852140	366128	0	0
T6	198132	70236	0	0
T10	3576	584	0	0
T11	15836	408	0	0
T12	1571448	514598	0	0
T17	9520	514	0	0
T18	1695246	970460	0	0
T34	0	21624	0	0
T38	0	20	0	0
T55	0	272748	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	389733124	0	0
T1	2806	64	0	0
T2	1758696	584272	0	0
T3	5324	64	0	0
T4	309908	48114	0	0
T5	852140	366128	0	0
T6	198132	42582	0	0
T10	3576	584	0	0
T11	15836	408	0	0
T12	1571448	514598	0	0
T17	9520	514	0	0
T18	1695246	970460	0	0
T34	0	20052	0	0
T38	0	20	0	0
T55	0	236642	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	389733124	0	0
T1	2806	64	0	0
T2	1758696	584272	0	0
T3	5324	64	0	0
T4	309908	48114	0	0
T5	852140	366128	0	0
T6	198132	42582	0	0
T10	3576	584	0	0
T11	15836	408	0	0
T12	1571448	514598	0	0
T17	9520	514	0	0
T18	1695246	970460	0	0
T34	0	20052	0	0
T38	0	20	0	0
T55	0	236642	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	413491688	0	0
T1	2806	64	0	0
T2	1758696	716452	0	0
T3	5324	64	0	0
T4	309908	51160	0	0
T5	852140	366128	0	0
T6	198132	70236	0	0
T10	3576	584	0	0
T11	15836	408	0	0
T12	1571448	514598	0	0
T17	9520	514	0	0
T18	1695246	970460	0	0
T34	0	21624	0	0
T38	0	20	0	0
T55	0	272748	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1459170744	1455785392	0	0
T1	5612	5344	0	0
T2	1758696	1758412	0	0
T3	5324	4940	0	0
T4	309908	309572	0	0
T5	852140	851936	0	0
T6	198132	197900	0	0
T10	3576	3372	0	0
T11	15836	13036	0	0
T12	1571448	1571388	0	0
T17	9520	9256	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	364792686	363946348	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	364792686	95117975	0	0
GntImpliesValid_A	364792686	95117975	0	0
GrantKnown_A	364792686	363946348	0	0
IdxKnown_A	364792686	363946348	0	0
IndexIsCorrect_A	364792686	95117975	0	0
NoReadyValidNoGrant_A	364792686	43996114	0	0
Priority_A	364792686	100917704	0	0
ReadyAndValidImplyGrant_A	364792686	95117975	0	0
ReqAndReadyImplyGrant_A	364792686	95117975	0	0
ReqImpliesValid_A	364792686	100917704	0	0
ValidKnown_A	364792686	363946348	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	95117975	0	0
T1	1403	32	0	0
T2	439674	125684	0	0
T3	1331	32	0	0
T4	77477	13378	0	0
T5	213035	101236	0	0
T6	49533	11864	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	95117975	0	0
T1	1403	32	0	0
T2	439674	125684	0	0
T3	1331	32	0	0
T4	77477	13378	0	0
T5	213035	101236	0	0
T6	49533	11864	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	95117975	0	0
T1	1403	32	0	0
T2	439674	125684	0	0
T3	1331	32	0	0
T4	77477	13378	0	0
T5	213035	101236	0	0
T6	49533	11864	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	43996114	0	0
T1	1403	128	0	0
T2	439674	51856	0	0
T3	1331	128	0	0
T4	77477	38012	0	0
T5	213035	128	0	0
T6	49533	15505	0	0
T10	894	128	0	0
T11	3959	768	0	0
T12	392862	530688	0	0
T17	2380	134	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	100917704	0	0
T1	1403	32	0	0
T2	439674	164243	0	0
T3	1331	32	0	0
T4	77477	14275	0	0
T5	213035	101236	0	0
T6	49533	19213	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	95117975	0	0
T1	1403	32	0	0
T2	439674	125684	0	0
T3	1331	32	0	0
T4	77477	13378	0	0
T5	213035	101236	0	0
T6	49533	11864	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	95117975	0	0
T1	1403	32	0	0
T2	439674	125684	0	0
T3	1331	32	0	0
T4	77477	13378	0	0
T5	213035	101236	0	0
T6	49533	11864	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	100917704	0	0
T1	1403	32	0	0
T2	439674	164243	0	0
T3	1331	32	0	0
T4	77477	14275	0	0
T5	213035	101236	0	0
T6	49533	19213	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	364792686	363946348	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	364792686	95118030	0	0
GntImpliesValid_A	364792686	95118030	0	0
GrantKnown_A	364792686	363946348	0	0
IdxKnown_A	364792686	363946348	0	0
IndexIsCorrect_A	364792686	95118030	0	0
NoReadyValidNoGrant_A	364792686	43996096	0	0
Priority_A	364792686	100917777	0	0
ReadyAndValidImplyGrant_A	364792686	95118030	0	0
ReqAndReadyImplyGrant_A	364792686	95118030	0	0
ReqImpliesValid_A	364792686	100917777	0	0
ValidKnown_A	364792686	363946348	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	95118030	0	0
T1	1403	32	0	0
T2	439674	125684	0	0
T3	1331	32	0	0
T4	77477	13378	0	0
T5	213035	101236	0	0
T6	49533	11864	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	95118030	0	0
T1	1403	32	0	0
T2	439674	125684	0	0
T3	1331	32	0	0
T4	77477	13378	0	0
T5	213035	101236	0	0
T6	49533	11864	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	95118030	0	0
T1	1403	32	0	0
T2	439674	125684	0	0
T3	1331	32	0	0
T4	77477	13378	0	0
T5	213035	101236	0	0
T6	49533	11864	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	43996096	0	0
T1	1403	128	0	0
T2	439674	51856	0	0
T3	1331	128	0	0
T4	77477	38012	0	0
T5	213035	128	0	0
T6	49533	15505	0	0
T10	894	128	0	0
T11	3959	768	0	0
T12	392862	530688	0	0
T17	2380	134	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	100917777	0	0
T1	1403	32	0	0
T2	439674	164243	0	0
T3	1331	32	0	0
T4	77477	14275	0	0
T5	213035	101236	0	0
T6	49533	19213	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	95118030	0	0
T1	1403	32	0	0
T2	439674	125684	0	0
T3	1331	32	0	0
T4	77477	13378	0	0
T5	213035	101236	0	0
T6	49533	11864	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	95118030	0	0
T1	1403	32	0	0
T2	439674	125684	0	0
T3	1331	32	0	0
T4	77477	13378	0	0
T5	213035	101236	0	0
T6	49533	11864	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	100917777	0	0
T1	1403	32	0	0
T2	439674	164243	0	0
T3	1331	32	0	0
T4	77477	14275	0	0
T5	213035	101236	0	0
T6	49533	19213	0	0
T10	894	292	0	0
T11	3959	204	0	0
T12	392862	129402	0	0
T17	2380	193	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	364792686	363946348	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	364792686	99748548	0	0
GntImpliesValid_A	364792686	99748548	0	0
GrantKnown_A	364792686	363946348	0	0
IdxKnown_A	364792686	363946348	0	0
IndexIsCorrect_A	364792686	99748548	0	0
NoReadyValidNoGrant_A	364792686	43010834	0	0
Priority_A	364792686	105828073	0	0
ReadyAndValidImplyGrant_A	364792686	99748548	0	0
ReqAndReadyImplyGrant_A	364792686	99748548	0	0
ReqImpliesValid_A	364792686	105828073	0	0
ValidKnown_A	364792686	363946348	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	99748548	0	0
T2	439674	166452	0	0
T3	1331	0	0	0
T4	77477	10679	0	0
T5	213035	81828	0	0
T6	49533	9427	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10026	0	0
T38	0	10	0	0
T55	0	118321	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	99748548	0	0
T2	439674	166452	0	0
T3	1331	0	0	0
T4	77477	10679	0	0
T5	213035	81828	0	0
T6	49533	9427	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10026	0	0
T38	0	10	0	0
T55	0	118321	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	99748548	0	0
T2	439674	166452	0	0
T3	1331	0	0	0
T4	77477	10679	0	0
T5	213035	81828	0	0
T6	49533	9427	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10026	0	0
T38	0	10	0	0
T55	0	118321	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	43010834	0	0
T2	439674	47783	0	0
T3	1331	0	0	0
T4	77477	31542	0	0
T5	213035	0	0	0
T6	49533	11641	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	524288	0	0
T17	2380	7	0	0
T18	847623	4064	0	0
T21	0	25	0	0
T34	0	30095	0	0
T38	0	25	0	0
T55	0	37302	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	105828073	0	0
T2	439674	193983	0	0
T3	1331	0	0	0
T4	77477	11305	0	0
T5	213035	81828	0	0
T6	49533	15905	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10812	0	0
T38	0	10	0	0
T55	0	136374	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	99748548	0	0
T2	439674	166452	0	0
T3	1331	0	0	0
T4	77477	10679	0	0
T5	213035	81828	0	0
T6	49533	9427	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10026	0	0
T38	0	10	0	0
T55	0	118321	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	99748548	0	0
T2	439674	166452	0	0
T3	1331	0	0	0
T4	77477	10679	0	0
T5	213035	81828	0	0
T6	49533	9427	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10026	0	0
T38	0	10	0	0
T55	0	118321	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	105828073	0	0
T2	439674	193983	0	0
T3	1331	0	0	0
T4	77477	11305	0	0
T5	213035	81828	0	0
T6	49533	15905	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10812	0	0
T38	0	10	0	0
T55	0	136374	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	364792686	363946348	0	0
CheckNGreaterZero_A	1044	1044	0	0
GntImpliesReady_A	364792686	99748571	0	0
GntImpliesValid_A	364792686	99748571	0	0
GrantKnown_A	364792686	363946348	0	0
IdxKnown_A	364792686	363946348	0	0
IndexIsCorrect_A	364792686	99748571	0	0
NoReadyValidNoGrant_A	364792686	43010796	0	0
Priority_A	364792686	105828134	0	0
ReadyAndValidImplyGrant_A	364792686	99748571	0	0
ReqAndReadyImplyGrant_A	364792686	99748571	0	0
ReqImpliesValid_A	364792686	105828134	0	0
ValidKnown_A	364792686	363946348	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044	1044	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	99748571	0	0
T2	439674	166452	0	0
T3	1331	0	0	0
T4	77477	10679	0	0
T5	213035	81828	0	0
T6	49533	9427	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10026	0	0
T38	0	10	0	0
T55	0	118321	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	99748571	0	0
T2	439674	166452	0	0
T3	1331	0	0	0
T4	77477	10679	0	0
T5	213035	81828	0	0
T6	49533	9427	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10026	0	0
T38	0	10	0	0
T55	0	118321	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	99748571	0	0
T2	439674	166452	0	0
T3	1331	0	0	0
T4	77477	10679	0	0
T5	213035	81828	0	0
T6	49533	9427	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10026	0	0
T38	0	10	0	0
T55	0	118321	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	43010796	0	0
T2	439674	47783	0	0
T3	1331	0	0	0
T4	77477	31542	0	0
T5	213035	0	0	0
T6	49533	11641	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	524288	0	0
T17	2380	7	0	0
T18	847623	4064	0	0
T21	0	25	0	0
T34	0	30095	0	0
T38	0	25	0	0
T55	0	37302	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	105828134	0	0
T2	439674	193983	0	0
T3	1331	0	0	0
T4	77477	11305	0	0
T5	213035	81828	0	0
T6	49533	15905	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10812	0	0
T38	0	10	0	0
T55	0	136374	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	99748571	0	0
T2	439674	166452	0	0
T3	1331	0	0	0
T4	77477	10679	0	0
T5	213035	81828	0	0
T6	49533	9427	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10026	0	0
T38	0	10	0	0
T55	0	118321	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	99748571	0	0
T2	439674	166452	0	0
T3	1331	0	0	0
T4	77477	10679	0	0
T5	213035	81828	0	0
T6	49533	9427	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10026	0	0
T38	0	10	0	0
T55	0	118321	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	105828134	0	0
T2	439674	193983	0	0
T3	1331	0	0	0
T4	77477	11305	0	0
T5	213035	81828	0	0
T6	49533	15905	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	127897	0	0
T17	2380	64	0	0
T18	847623	485230	0	0
T34	0	10812	0	0
T38	0	10	0	0
T55	0	136374	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792686	363946348	0	0
T1	1403	1336	0	0
T2	439674	439603	0	0
T3	1331	1235	0	0
T4	77477	77393	0	0
T5	213035	212984	0	0
T6	49533	49475	0	0
T10	894	843	0	0
T11	3959	3259	0	0
T12	392862	392847	0	0
T17	2380	2314	0	0