Unified Coverage Report :: Module :: flash_mp

Module : flash_mp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.64	100.00	98.56			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_mp	99.64	100.00	98.56			100.00	100.00

---

Module Instance : tb.dut.u_flash_mp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.64	100.00	98.56			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_hw_sel	100.00	100.00				100.00
u_sw_sel	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_mp

	Line No.	Total	Covered	Percent
TOTAL		76	76	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
ALWAYS	185	0	0
ALWAYS	185	2	2	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	206	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
ALWAYS	240	10	10	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	274	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
CONT_ASSIGN	289	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	291	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	296	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
ALWAYS	307	6	6	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	375	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
78	1	1
79	1	1
80	1	1
100	1	1
104	1	1
105	1	1
121	1	1
129	1	1
132	1	1
149	9	9
174	1	1
179	1	1
180	1	1
185	1	1
186	1	1
191	1	1
195	1	1
198	1	1
201	1	1
204	1	1
206	1	1
209	1	1
212	1	1
215	1	1
240	1	1
241	1	1
242	1	1
243	1	1
245	1	1
248	1	1
249	1	1
			MISSING_ELSE
			MISSING_ELSE
254	1	1
255	1	1
257	1	1
262	1	1
263	1	1
266	1	1
269	1	1
270	1	1
271	1	1
273	1	1
274	1	1
277	1	1
278	1	1
281	1	1
289	1	1
290	1	1
291	1	1
292	1	1
293	1	1
294	1	1
295	1	1
296	1	1
301	1	1
307	1	1
308	1	1
309	1	1
310	1	1
311	1	1
312	1	1
			MISSING_ELSE
316	1	1
317	1	1
318	1	1
319	1	1
324	1	1
325	1	1
326	1	1
375	1	1

---

Cond Coverage for Module : flash_mp

	Total	Covered	Percent
Conditions	139	137	98.56
Logical	139	137	98.56
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (if_sel_i == HwSel)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (req_part_i == FlashPartData)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 EXPRESSION (req_part_i == FlashPartInfo)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       129
 EXPRESSION (data_part_sel ? flash_ctrl_pkg::DataPartitionEndAddr : flash_ctrl_pkg::InfoPartitionEndAddr[info_sel_i])
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (req_i & ((page_addr > end_addr) | bank_invalid | addr_ovfl_i))
             --1--   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T55,T28,T33

 LINE       132
 SUB-EXPRESSION ((page_addr > end_addr) | bank_invalid | addr_ovfl_i)
                 -----------1----------   ------2-----   -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T31,T79,T80
0	1	0	Unreachable
1	0	0	Covered	T2,T4,T5

 LINE       154
 EXPRESSION (req_i & ((~hw_sel)))
             --1--   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T10

 LINE       164
 EXPRESSION (req_i & hw_sel)
             --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T10
1	1	Covered	T1,T2,T3

 LINE       174
 EXPRESSION (hw_sel ? hw_sel_cfg : sw_sel_cfg)
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       186
 EXPRESSION ((bank_addr == i[0]) & bank_cfgs_i[i].q & ((~hw_sel)))
             ---------1---------   --------2-------   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T17,T18
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T101,T106
1	1	1	Covered	T12,T17,T18

 LINE       186
 SUB-EXPRESSION (bank_addr == i[0])
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       204
 EXPRESSION (bk_erase_i & ((|bk_erase_en)))
             -----1----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T12,T17,T18
1	0	Covered	T18,T27,T111
1	1	Covered	T18,T27,T41

 LINE       215
 EXPRESSION (req_i & data_part_sel & ( ~ (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en) ))
             --1--   ------2------   -----------------------------------3-----------------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T5,T6,T18

 LINE       215
 SUB-EXPRESSION (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en)
                 -----1----   ------2-----   --------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T18,T27,T41
0	0	1	0	Covered	T12,T18,T22
0	1	0	0	Covered	T2,T5,T12
1	0	0	0	Covered	T2,T4,T12

 LINE       242
 EXPRESSION (hw_sel && req_i)
             ---1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       245
 EXPRESSION 
 Number  Term
      1  (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr) && 
      2  (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel) && 
      3  (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       245
 SUB-EXPRESSION (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr)
                -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       245
 SUB-EXPRESSION (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel)
                -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T13
1	Covered	T1,T2,T3

 LINE       245
 SUB-EXPRESSION (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase)
                --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       263
 EXPRESSION (hw_sel ? hw_page_cfg : info_page_cfgs_i[bank_addr][info_sel_i][info_page_addr])
             ---1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (info_part_sel & bk_erase_i & ((|bk_erase_en)))
             ------1------   -----2----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T41,T225,T66
1	0	1	Covered	T18,T27,T40
1	1	0	Covered	T18,T27,T111
1	1	1	Covered	T18,T27,T111

 LINE       281
 EXPRESSION (req_i & info_part_sel & ( ~ (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en) ))
             --1--   ------2------   -----------------------------------3-----------------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T4,T11

 LINE       281
 SUB-EXPRESSION (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en)
                 -----1----   ------2-----   --------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T18,T27,T111
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Covered	T2,T5,T12
1	0	0	0	Covered	T1,T2,T3

 LINE       289
 EXPRESSION (req_i & (data_rd_en | info_rd_en))
             --1--   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T2,T4,T10
1	1	Covered	T1,T2,T3

 LINE       289
 SUB-EXPRESSION (data_rd_en | info_rd_en)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T12

 LINE       290
 EXPRESSION (req_i & (data_prog_en | info_prog_en))
             --1--   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T12

 LINE       290
 SUB-EXPRESSION (data_prog_en | info_prog_en)
                 ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T12
1	0	Covered	T2,T5,T12

 LINE       291
 EXPRESSION (req_i & (data_pg_erase_en | info_pg_erase_en))
             --1--   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T18,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T11,T12

 LINE       291
 SUB-EXPRESSION (data_pg_erase_en | info_pg_erase_en)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T12,T18,T22

 LINE       292
 EXPRESSION (req_i & (data_bk_erase_en | info_bk_erase_en))
             --1--   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T27,T41
1	0	Covered	T1,T2,T3
1	1	Covered	T18,T27,T41

 LINE       292
 SUB-EXPRESSION (data_bk_erase_en | info_bk_erase_en)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T41,T225,T66

 LINE       293
 EXPRESSION (req_i & (data_scramble_en | info_scramble_en))
             --1--   ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T10,T11
1	1	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (data_scramble_en | info_scramble_en)
                 --------1-------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5

 LINE       294
 EXPRESSION (req_i & (data_ecc_en | info_ecc_en))
             --1--   -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T10,T11
1	1	Covered	T1,T2,T3

 LINE       294
 SUB-EXPRESSION (data_ecc_en | info_ecc_en)
                 -----1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (req_i & (data_he_en | info_he_en))
             --1--   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T10
1	0	Covered	T2,T4,T11
1	1	Covered	T1,T2,T3

 LINE       295
 SUB-EXPRESSION (data_he_en | info_he_en)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5

 LINE       296
 EXPRESSION (rd_o | prog_o | pg_erase_o | bk_erase_o)
             --1-   ---2--   -----3----   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T18,T27,T41
0	0	1	0	Covered	T10,T11,T12
0	1	0	0	Covered	T2,T5,T12
1	0	0	0	Covered	T1,T2,T3

 LINE       316
 EXPRESSION (rd_done_i | txn_err)
             ----1----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T11
1	0	Covered	T1,T2,T3

 LINE       317
 EXPRESSION (prog_done_i | txn_err)
             -----1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T11
1	0	Covered	T2,T5,T12

 LINE       318
 EXPRESSION (erase_done_i | txn_err)
             ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T11
1	0	Covered	T10,T12,T18

 LINE       324
 EXPRESSION (pg_erase_o | bk_erase_o)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T27,T41
1	0	Covered	T10,T11,T12

 LINE       325
 EXPRESSION (erase_valid & erase_suspend_i)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T154,T155,T159
1	0	Covered	T10,T11,T12
1	1	Covered	T45,T81,T82

 LINE       326
 EXPRESSION ((erase_suspend_i & ((~erase_valid))) | (erase_suspend_o & erase_done_o))
             ------------------1-----------------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T81,T82
1	0	Covered	T154,T155,T159

 LINE       326
 SUB-EXPRESSION (erase_suspend_i & ((~erase_valid)))
                 -------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T81,T82
1	1	Covered	T154,T155,T159

 LINE       326
 SUB-EXPRESSION (erase_suspend_o & erase_done_o)
                 -------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T10
1	0	Covered	T45,T81,T82
1	1	Covered	T45,T81,T82

---

Branch Coverage for Module : flash_mp

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	129	2	2	100.00
TERNARY	174	2	2	100.00
TERNARY	263	2	2	100.00
IF	242	2	2	100.00
IF	307	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	129	(data_part_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	174	(hw_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	263	(hw_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	242	if ((hw_sel && req_i))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	if ((!rst_ni))
-2-:	309	if (txn_err)
-3-:	311	if (no_allowed_txn)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T11
0	0	1	Covered	T2,T4,T11
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_mp

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BankEraseData_A	364792856	7538219	0	0
BankEraseInfo_A	364792856	11469500	0	0
DataReqToInfo_A	364792856	233597214	0	0
InReqOutReq_A	364792856	262117337	0	0
InfoReqToData_A	364792856	28520123	0	0
NoReqWhenErr_A	357355091	116801	0	0
bkEraseEnOnehot_A	364792856	19007719	0	0
hwInfoRuleOnehot_A	364792856	147121873	0	0
invalidReqOnehot_A	364792856	262000490	0	0
requestTypesOnehot_A	364792856	262000490	0	0

BankEraseData_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792856	7538219	0	0
T41	73296	65540	0	0
T44	227355	0	0	0
T66	0	393240	0	0
T67	0	131080	0	0
T68	0	65540	0	0
T85	79054	0	0	0
T101	407980	0	0	0
T104	0	262160	0	0
T154	0	196872	0	0
T162	1504	0	0	0
T169	3611	0	0	0
T197	7986	0	0	0
T219	0	65540	0	0
T225	0	65540	0	0
T228	0	65540	0	0
T229	0	65540	0	0
T230	46896	0	0	0
T231	1018	0	0	0
T232	865	0	0	0

BankEraseInfo_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792856	11469500	0	0
T18	847623	393240	0	0
T21	2730	0	0	0
T22	5683	0	0	0
T27	0	655400	0	0
T34	59475	0	0	0
T38	1058	0	0	0
T42	1251	0	0	0
T47	1735	0	0	0
T55	384926	0	0	0
T61	240450	0	0	0
T83	1693	0	0	0
T111	0	458780	0	0
T112	0	65540	0	0
T113	0	131080	0	0
T114	0	65540	0	0
T115	0	917560	0	0
T128	0	65540	0	0
T140	0	393240	0	0
T143	0	786480	0	0

DataReqToInfo_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792856	233597214	0	0
T2	439674	363674	0	0
T3	1331	0	0	0
T4	77477	51055	0	0
T5	213035	160875	0	0
T6	49533	22276	0	0
T10	894	0	0	0
T11	3959	0	0	0
T12	392862	360652	0	0
T17	2380	238	0	0
T18	847623	10836	0	0
T34	0	36669	0	0
T38	0	35	0	0
T55	0	308347	0	0

InReqOutReq_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792856	262117337	0	0
T1	1403	160	0	0
T2	439674	380708	0	0
T3	1331	160	0	0
T4	77477	54410	0	0
T5	213035	183620	0	0
T6	49533	29179	0	0
T10	894	420	0	0
T11	3959	974	0	0
T12	392862	362798	0	0
T17	2380	398	0	0

InfoReqToData_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792856	28520123	0	0
T1	1403	160	0	0
T2	439674	17034	0	0
T3	1331	160	0	0
T4	77477	3355	0	0
T5	213035	22745	0	0
T6	49533	6903	0	0
T10	894	420	0	0
T11	3959	974	0	0
T12	392862	21452	0	0
T17	2380	160	0	0

NoReqWhenErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357355091	116801	0	0
T2	439674	658	0	0
T3	1331	0	0	0
T4	77477	236	0	0
T5	213035	428	0	0
T6	49533	458	0	0
T10	894	0	0	0
T11	2752	0	0	0
T12	392862	0	0	0
T17	2380	0	0	0
T18	847623	1114	0	0
T22	0	16	0	0
T34	0	232	0	0
T35	0	700	0	0
T55	0	616	0	0
T61	0	242	0	0

bkEraseEnOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792856	19007719	0	0
T18	847623	393240	0	0
T21	2730	0	0	0
T22	5683	0	0	0
T27	0	655400	0	0
T34	59475	0	0	0
T38	1058	0	0	0
T41	0	65540	0	0
T42	1251	0	0	0
T47	1735	0	0	0
T55	384926	0	0	0
T61	240450	0	0	0
T66	0	393240	0	0
T67	0	131080	0	0
T68	0	65540	0	0
T83	1693	0	0	0
T104	0	262160	0	0
T111	0	458780	0	0
T225	0	65540	0	0
T228	0	65540	0	0

hwInfoRuleOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792856	147121873	0	0
T1	1403	160	0	0
T2	439674	160	0	0
T3	1331	160	0	0
T4	77477	160	0	0
T5	213035	160	0	0
T6	49533	160	0	0
T10	894	160	0	0
T11	3959	974	0	0
T12	392862	362798	0	0
T17	2380	160	0	0

invalidReqOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792856	262000490	0	0
T1	1403	160	0	0
T2	439674	380050	0	0
T3	1331	160	0	0
T4	77477	54174	0	0
T5	213035	183192	0	0
T6	49533	28721	0	0
T10	894	420	0	0
T11	3959	973	0	0
T12	392862	362798	0	0
T17	2380	398	0	0

requestTypesOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364792856	262000490	0	0
T1	1403	160	0	0
T2	439674	380050	0	0
T3	1331	160	0	0
T4	77477	54174	0	0
T5	213035	183192	0	0
T6	49533	28721	0	0
T10	894	420	0	0
T11	3959	973	0	0
T12	392862	362798	0	0
T17	2380	398	0	0