Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	367720706	4097	0	0
addr_rd_A	367720706	1829	0	0
bank0_info0_page_cfg_0_rd_A	367720706	3742	0	0
bank0_info0_page_cfg_1_rd_A	367720706	3913	0	0
bank0_info0_page_cfg_2_rd_A	367720706	3325	0	0
bank0_info0_page_cfg_3_rd_A	367720706	3798	0	0
bank0_info0_page_cfg_4_rd_A	367720706	3922	0	0
bank0_info0_page_cfg_5_rd_A	367720706	3422	0	0
bank0_info0_page_cfg_6_rd_A	367720706	3584	0	0
bank0_info0_page_cfg_7_rd_A	367720706	3710	0	0
bank0_info0_page_cfg_8_rd_A	367720706	4023	0	0
bank0_info0_page_cfg_9_rd_A	367720706	3961	0	0
bank0_info0_regwen_0_rd_A	367720706	2265	0	0
bank0_info0_regwen_1_rd_A	367720706	1658	0	0
bank0_info0_regwen_2_rd_A	367720706	1921	0	0
bank0_info0_regwen_3_rd_A	367720706	2370	0	0
bank0_info0_regwen_4_rd_A	367720706	2268	0	0
bank0_info0_regwen_5_rd_A	367720706	2418	0	0
bank0_info0_regwen_6_rd_A	367720706	1891	0	0
bank0_info0_regwen_7_rd_A	367720706	1854	0	0
bank0_info0_regwen_8_rd_A	367720706	2366	0	0
bank0_info0_regwen_9_rd_A	367720706	2344	0	0
bank0_info1_page_cfg_rd_A	367720706	3943	0	0
bank0_info1_regwen_rd_A	367720706	2175	0	0
bank0_info2_page_cfg_0_rd_A	367720706	3600	0	0
bank0_info2_page_cfg_1_rd_A	367720706	3397	0	0
bank0_info2_regwen_0_rd_A	367720706	2395	0	0
bank0_info2_regwen_1_rd_A	367720706	1740	0	0
bank1_info0_page_cfg_0_rd_A	367720706	3622	0	0
bank1_info0_page_cfg_1_rd_A	367720706	3871	0	0
bank1_info0_page_cfg_2_rd_A	367720706	3237	0	0
bank1_info0_page_cfg_3_rd_A	367720706	3697	0	0
bank1_info0_page_cfg_4_rd_A	367720706	3585	0	0
bank1_info0_page_cfg_5_rd_A	367720706	4141	0	0
bank1_info0_page_cfg_6_rd_A	367720706	3407	0	0
bank1_info0_page_cfg_7_rd_A	367720706	4236	0	0
bank1_info0_page_cfg_8_rd_A	367720706	3717	0	0
bank1_info0_page_cfg_9_rd_A	367720706	3129	0	0
bank1_info0_regwen_0_rd_A	367720706	1802	0	0
bank1_info0_regwen_1_rd_A	367720706	2247	0	0
bank1_info0_regwen_2_rd_A	367720706	1806	0	0
bank1_info0_regwen_3_rd_A	367720706	2330	0	0
bank1_info0_regwen_4_rd_A	367720706	2280	0	0
bank1_info0_regwen_5_rd_A	367720706	1700	0	0
bank1_info0_regwen_6_rd_A	367720706	1807	0	0
bank1_info0_regwen_7_rd_A	367720706	1252	0	0
bank1_info0_regwen_8_rd_A	367720706	2291	0	0
bank1_info0_regwen_9_rd_A	367720706	2330	0	0
bank1_info1_page_cfg_rd_A	367720706	3778	0	0
bank1_info1_regwen_rd_A	367720706	2376	0	0
bank1_info2_page_cfg_0_rd_A	367720706	3190	0	0
bank1_info2_page_cfg_1_rd_A	367720706	3551	0	0
bank1_info2_regwen_0_rd_A	367720706	1261	0	0
bank1_info2_regwen_1_rd_A	367720706	1812	0	0
bank_cfg_regwen_rd_A	367720706	2173	0	0
default_region_rd_A	367720706	3756	0	0
exec_rd_A	367720706	1849	0	0
fifo_lvl_rd_A	367720706	2163	0	0
fifo_rst_rd_A	367720706	2287	0	0
hw_info_cfg_override_rd_A	367720706	2087	0	0
intr_enable_rd_A	367720706	3411	0	0
mp_region_0_rd_A	367720706	2420	0	0
mp_region_1_rd_A	367720706	2136	0	0
mp_region_2_rd_A	367720706	1469	0	0
mp_region_3_rd_A	367720706	2466	0	0
mp_region_4_rd_A	367720706	2506	0	0
mp_region_5_rd_A	367720706	2615	0	0
mp_region_6_rd_A	367720706	2503	0	0
mp_region_7_rd_A	367720706	2467	0	0
mp_region_cfg_0_rd_A	367720706	3518	0	0
mp_region_cfg_1_rd_A	367720706	3208	0	0
mp_region_cfg_2_rd_A	367720706	2680	0	0
mp_region_cfg_3_rd_A	367720706	3865	0	0
mp_region_cfg_4_rd_A	367720706	3909	0	0
mp_region_cfg_5_rd_A	367720706	3751	0	0
mp_region_cfg_6_rd_A	367720706	3757	0	0
mp_region_cfg_7_rd_A	367720706	3854	0	0
phy_alert_cfg_rd_A	367720706	1404	0	0
region_cfg_regwen_0_rd_A	367720706	2268	0	0
region_cfg_regwen_1_rd_A	367720706	2231	0	0
region_cfg_regwen_2_rd_A	367720706	1243	0	0
region_cfg_regwen_3_rd_A	367720706	1675	0	0
region_cfg_regwen_4_rd_A	367720706	1735	0	0
region_cfg_regwen_5_rd_A	367720706	2433	0	0
region_cfg_regwen_6_rd_A	367720706	2276	0	0
region_cfg_regwen_7_rd_A	367720706	1679	0	0
scratch_rd_A	367720706	2189	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	4097	0	0
T65	6030	2	0	0
T99	4101	285	0	0
T100	3542	214	0	0
T215	2964	200	0	0
T216	84720	2	0	0
T233	77376	2	0	0
T236	5688	113	0	0
T237	6318	225	0	0
T238	9801	9	0	0
T239	5642	429	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1829	0	0
T65	6030	7	0	0
T216	84720	69	0	0
T233	77376	51	0	0
T238	9801	12	0	0
T255	18824	32	0	0
T256	9839	42	0	0
T259	19572	40	0	0
T260	18562	42	0	0
T272	80572	65	0	0
T310	6061	16	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3742	0	0
T216	84720	228	0	0
T233	77376	357	0	0
T238	9801	46	0	0
T255	18824	19	0	0
T256	9839	6	0	0
T259	19572	72	0	0
T260	18562	25	0	0
T272	80572	123	0	0
T274	75332	171	0	0
T310	6061	21	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3913	0	0
T65	6030	24	0	0
T216	84720	311	0	0
T233	77376	298	0	0
T238	9801	29	0	0
T255	18824	77	0	0
T256	9839	19	0	0
T259	19572	7	0	0
T260	18562	16	0	0
T272	80572	171	0	0
T310	6061	7	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3325	0	0
T65	6030	3	0	0
T216	84720	283	0	0
T233	77376	273	0	0
T238	9801	48	0	0
T255	18824	22	0	0
T256	9839	48	0	0
T259	19572	28	0	0
T260	18562	4	0	0
T272	80572	168	0	0
T310	6061	10	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3798	0	0
T65	6030	8	0	0
T216	84720	322	0	0
T233	77376	326	0	0
T238	9801	36	0	0
T255	18824	26	0	0
T256	9839	14	0	0
T259	19572	54	0	0
T260	18562	16	0	0
T272	80572	204	0	0
T310	6061	8	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3922	0	0
T65	6030	29	0	0
T216	84720	232	0	0
T233	77376	229	0	0
T238	9801	48	0	0
T255	18824	83	0	0
T256	9839	43	0	0
T259	19572	76	0	0
T260	18562	29	0	0
T272	80572	157	0	0
T310	6061	5	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3422	0	0
T65	6030	18	0	0
T216	84720	292	0	0
T233	77376	195	0	0
T238	9801	57	0	0
T255	18824	101	0	0
T256	9839	9	0	0
T259	19572	80	0	0
T260	18562	31	0	0
T272	80572	220	0	0
T310	6061	70	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3584	0	0
T65	6030	17	0	0
T216	84720	356	0	0
T233	77376	321	0	0
T238	9801	36	0	0
T255	18824	22	0	0
T259	19572	60	0	0
T260	18562	29	0	0
T272	80572	191	0	0
T274	75332	133	0	0
T310	6061	13	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3710	0	0
T65	6030	14	0	0
T216	84720	318	0	0
T233	77376	237	0	0
T238	9801	39	0	0
T255	18824	45	0	0
T256	9839	13	0	0
T259	19572	82	0	0
T260	18562	47	0	0
T272	80572	193	0	0
T310	6061	63	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	4023	0	0
T65	6030	6	0	0
T216	84720	221	0	0
T233	77376	404	0	0
T238	9801	75	0	0
T255	18824	25	0	0
T256	9839	14	0	0
T259	19572	36	0	0
T260	18562	8	0	0
T272	80572	163	0	0
T310	6061	35	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3961	0	0
T65	6030	12	0	0
T216	84720	357	0	0
T233	77376	300	0	0
T238	9801	41	0	0
T255	18824	59	0	0
T256	9839	41	0	0
T259	19572	50	0	0
T260	18562	26	0	0
T272	80572	224	0	0
T310	6061	12	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2265	0	0
T65	6030	4	0	0
T216	84720	78	0	0
T233	77376	79	0	0
T238	9801	21	0	0
T255	18824	35	0	0
T256	9839	10	0	0
T259	19572	57	0	0
T260	18562	8	0	0
T272	80572	68	0	0
T310	6061	9	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1658	0	0
T65	6030	5	0	0
T216	84720	62	0	0
T233	77376	86	0	0
T238	9801	15	0	0
T255	18824	52	0	0
T256	9839	10	0	0
T259	19572	21	0	0
T260	18562	38	0	0
T272	80572	44	0	0
T310	6061	11	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1921	0	0
T65	6030	8	0	0
T216	84720	45	0	0
T233	77376	90	0	0
T238	9801	10	0	0
T255	18824	65	0	0
T256	9839	28	0	0
T259	19572	40	0	0
T260	18562	46	0	0
T272	80572	58	0	0
T310	6061	4	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2370	0	0
T216	84720	94	0	0
T233	77376	70	0	0
T238	9801	13	0	0
T255	18824	35	0	0
T256	9839	11	0	0
T259	19572	30	0	0
T260	18562	15	0	0
T272	80572	46	0	0
T274	75332	56	0	0
T310	6061	11	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2268	0	0
T65	6030	9	0	0
T216	84720	76	0	0
T233	77376	55	0	0
T238	9801	12	0	0
T255	18824	28	0	0
T256	9839	14	0	0
T259	19572	34	0	0
T260	18562	42	0	0
T272	80572	50	0	0
T310	6061	18	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2418	0	0
T216	84720	69	0	0
T233	77376	64	0	0
T238	9801	20	0	0
T255	18824	68	0	0
T256	9839	38	0	0
T259	19572	65	0	0
T260	18562	42	0	0
T272	80572	62	0	0
T274	75332	48	0	0
T310	6061	9	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1891	0	0
T65	6030	11	0	0
T216	84720	72	0	0
T233	77376	84	0	0
T238	9801	9	0	0
T255	18824	57	0	0
T256	9839	29	0	0
T259	19572	47	0	0
T260	18562	55	0	0
T272	80572	31	0	0
T310	6061	13	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1854	0	0
T65	6030	10	0	0
T216	84720	63	0	0
T233	77376	98	0	0
T238	9801	22	0	0
T255	18824	49	0	0
T256	9839	14	0	0
T259	19572	68	0	0
T260	18562	7	0	0
T272	80572	46	0	0
T310	6061	3	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2366	0	0
T216	84720	99	0	0
T233	77376	96	0	0
T238	9801	17	0	0
T255	18824	54	0	0
T259	19572	22	0	0
T260	18562	13	0	0
T272	80572	45	0	0
T274	75332	24	0	0
T310	6061	12	0	0
T311	6688	6	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2344	0	0
T65	6030	10	0	0
T216	84720	84	0	0
T233	77376	75	0	0
T238	9801	19	0	0
T255	18824	33	0	0
T256	9839	35	0	0
T259	19572	47	0	0
T260	18562	19	0	0
T272	80572	26	0	0
T310	6061	8	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3943	0	0
T65	6030	11	0	0
T216	84720	300	0	0
T233	77376	311	0	0
T238	9801	14	0	0
T255	18824	26	0	0
T256	9839	34	0	0
T259	19572	42	0	0
T260	18562	13	0	0
T272	80572	159	0	0
T310	6061	9	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2175	0	0
T65	6030	9	0	0
T216	84720	62	0	0
T233	77376	71	0	0
T238	9801	9	0	0
T255	18824	43	0	0
T256	9839	12	0	0
T259	19572	70	0	0
T260	18562	17	0	0
T272	80572	28	0	0
T310	6061	2	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3600	0	0
T65	6030	11	0	0
T216	84720	206	0	0
T233	77376	321	0	0
T238	9801	55	0	0
T255	18824	42	0	0
T259	19572	12	0	0
T260	18562	42	0	0
T272	80572	205	0	0
T274	75332	105	0	0
T310	6061	74	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3397	0	0
T65	6030	1	0	0
T216	84720	391	0	0
T233	77376	413	0	0
T238	9801	24	0	0
T255	18824	43	0	0
T256	9839	33	0	0
T259	19572	48	0	0
T260	18562	23	0	0
T272	80572	175	0	0
T310	6061	57	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2395	0	0
T65	6030	1	0	0
T216	84720	76	0	0
T233	77376	79	0	0
T238	9801	18	0	0
T255	18824	82	0	0
T256	9839	33	0	0
T259	19572	70	0	0
T260	18562	4	0	0
T272	80572	37	0	0
T310	6061	8	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1740	0	0
T65	6030	4	0	0
T216	84720	74	0	0
T233	77376	87	0	0
T238	9801	7	0	0
T255	18824	37	0	0
T256	9839	9	0	0
T259	19572	12	0	0
T260	18562	6	0	0
T272	80572	46	0	0
T310	6061	15	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3622	0	0
T216	84720	297	0	0
T233	77376	225	0	0
T238	9801	67	0	0
T255	18824	30	0	0
T256	9839	43	0	0
T259	19572	61	0	0
T260	18562	13	0	0
T272	80572	136	0	0
T274	75332	163	0	0
T310	6061	34	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3871	0	0
T65	6030	7	0	0
T216	84720	339	0	0
T233	77376	301	0	0
T238	9801	5	0	0
T255	18824	9	0	0
T256	9839	7	0	0
T259	19572	54	0	0
T260	18562	25	0	0
T272	80572	148	0	0
T310	6061	46	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3237	0	0
T65	6030	5	0	0
T216	84720	252	0	0
T233	77376	266	0	0
T238	9801	16	0	0
T255	18824	55	0	0
T256	9839	23	0	0
T259	19572	60	0	0
T260	18562	20	0	0
T272	80572	168	0	0
T310	6061	63	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3697	0	0
T65	6030	5	0	0
T216	84720	192	0	0
T233	77376	303	0	0
T238	9801	29	0	0
T255	18824	55	0	0
T256	9839	5	0	0
T259	19572	28	0	0
T260	18562	24	0	0
T272	80572	207	0	0
T310	6061	26	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3585	0	0
T65	6030	3	0	0
T216	84720	340	0	0
T233	77376	336	0	0
T238	9801	62	0	0
T255	18824	34	0	0
T256	9839	10	0	0
T259	19572	33	0	0
T260	18562	5	0	0
T272	80572	185	0	0
T310	6061	38	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	4141	0	0
T65	6030	21	0	0
T216	84720	389	0	0
T233	77376	393	0	0
T238	9801	12	0	0
T255	18824	45	0	0
T256	9839	50	0	0
T259	19572	33	0	0
T260	18562	20	0	0
T272	80572	175	0	0
T310	6061	35	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3407	0	0
T65	6030	2	0	0
T216	84720	333	0	0
T233	77376	256	0	0
T238	9801	67	0	0
T255	18824	35	0	0
T256	9839	7	0	0
T259	19572	51	0	0
T260	18562	24	0	0
T272	80572	159	0	0
T310	6061	63	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	4236	0	0
T216	84720	360	0	0
T233	77376	295	0	0
T238	9801	30	0	0
T255	18824	49	0	0
T256	9839	5	0	0
T259	19572	46	0	0
T260	18562	32	0	0
T272	80572	204	0	0
T274	75332	198	0	0
T310	6061	33	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3717	0	0
T65	6030	8	0	0
T216	84720	237	0	0
T233	77376	262	0	0
T238	9801	22	0	0
T255	18824	34	0	0
T256	9839	21	0	0
T259	19572	36	0	0
T260	18562	8	0	0
T272	80572	233	0	0
T310	6061	37	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3129	0	0
T65	6030	10	0	0
T216	84720	331	0	0
T233	77376	322	0	0
T238	9801	20	0	0
T255	18824	55	0	0
T256	9839	27	0	0
T259	19572	33	0	0
T260	18562	17	0	0
T272	80572	156	0	0
T310	6061	45	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1802	0	0
T65	6030	10	0	0
T216	84720	62	0	0
T233	77376	70	0	0
T238	9801	20	0	0
T255	18824	9	0	0
T256	9839	4	0	0
T259	19572	43	0	0
T260	18562	32	0	0
T272	80572	38	0	0
T310	6061	5	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2247	0	0
T216	84720	87	0	0
T233	77376	61	0	0
T238	9801	22	0	0
T255	18824	72	0	0
T256	9839	2	0	0
T259	19572	74	0	0
T260	18562	45	0	0
T272	80572	35	0	0
T274	75332	41	0	0
T310	6061	5	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1806	0	0
T216	84720	85	0	0
T233	77376	103	0	0
T238	9801	17	0	0
T255	18824	1	0	0
T256	9839	22	0	0
T259	19572	29	0	0
T260	18562	8	0	0
T272	80572	50	0	0
T274	75332	46	0	0
T310	6061	13	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2330	0	0
T65	6030	15	0	0
T216	84720	90	0	0
T233	77376	72	0	0
T238	9801	18	0	0
T255	18824	28	0	0
T256	9839	23	0	0
T259	19572	41	0	0
T260	18562	9	0	0
T272	80572	26	0	0
T310	6061	8	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2280	0	0
T216	84720	65	0	0
T233	77376	79	0	0
T238	9801	16	0	0
T255	18824	52	0	0
T256	9839	27	0	0
T259	19572	30	0	0
T260	18562	27	0	0
T272	80572	40	0	0
T274	75332	52	0	0
T310	6061	7	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1700	0	0
T65	6030	4	0	0
T216	84720	81	0	0
T233	77376	55	0	0
T238	9801	21	0	0
T255	18824	53	0	0
T256	9839	15	0	0
T259	19572	18	0	0
T260	18562	3	0	0
T272	80572	33	0	0
T310	6061	7	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1807	0	0
T65	6030	11	0	0
T216	84720	79	0	0
T233	77376	81	0	0
T238	9801	21	0	0
T255	18824	22	0	0
T256	9839	8	0	0
T259	19572	60	0	0
T260	18562	34	0	0
T272	80572	57	0	0
T274	75332	33	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1252	0	0
T65	6030	8	0	0
T216	84720	66	0	0
T233	77376	74	0	0
T238	9801	11	0	0
T255	18824	46	0	0
T256	9839	36	0	0
T259	19572	55	0	0
T260	18562	8	0	0
T272	80572	66	0	0
T310	6061	4	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2291	0	0
T216	84720	83	0	0
T233	77376	74	0	0
T238	9801	13	0	0
T255	18824	14	0	0
T256	9839	3	0	0
T259	19572	65	0	0
T260	18562	12	0	0
T272	80572	52	0	0
T274	75332	23	0	0
T311	6688	12	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2330	0	0
T216	84720	50	0	0
T233	77376	107	0	0
T238	9801	24	0	0
T255	18824	74	0	0
T256	9839	54	0	0
T259	19572	83	0	0
T260	18562	15	0	0
T272	80572	36	0	0
T274	75332	33	0	0
T310	6061	4	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3778	0	0
T65	6030	14	0	0
T216	84720	253	0	0
T233	77376	327	0	0
T238	9801	14	0	0
T255	18824	16	0	0
T259	19572	54	0	0
T260	18562	27	0	0
T272	80572	160	0	0
T274	75332	128	0	0
T310	6061	5	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2376	0	0
T216	84720	93	0	0
T233	77376	74	0	0
T238	9801	21	0	0
T255	18824	14	0	0
T256	9839	49	0	0
T259	19572	70	0	0
T260	18562	28	0	0
T272	80572	44	0	0
T274	75332	40	0	0
T310	6061	4	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3190	0	0
T65	6030	20	0	0
T216	84720	328	0	0
T233	77376	224	0	0
T238	9801	17	0	0
T255	18824	19	0	0
T256	9839	29	0	0
T259	19572	19	0	0
T260	18562	23	0	0
T272	80572	219	0	0
T310	6061	9	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3551	0	0
T65	6030	25	0	0
T216	84720	371	0	0
T233	77376	325	0	0
T238	9801	25	0	0
T255	18824	31	0	0
T256	9839	25	0	0
T259	19572	62	0	0
T260	18562	47	0	0
T272	80572	157	0	0
T310	6061	35	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1261	0	0
T65	6030	9	0	0
T216	84720	84	0	0
T233	77376	84	0	0
T238	9801	15	0	0
T255	18824	20	0	0
T256	9839	5	0	0
T259	19572	33	0	0
T260	18562	32	0	0
T272	80572	69	0	0
T310	6061	7	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1812	0	0
T65	6030	4	0	0
T216	84720	98	0	0
T233	77376	71	0	0
T238	9801	11	0	0
T255	18824	37	0	0
T256	9839	46	0	0
T259	19572	59	0	0
T260	18562	20	0	0
T272	80572	29	0	0
T310	6061	12	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2173	0	0
T65	6030	8	0	0
T216	84720	84	0	0
T233	77376	79	0	0
T238	9801	9	0	0
T255	18824	61	0	0
T256	9839	6	0	0
T259	19572	43	0	0
T260	18562	31	0	0
T272	80572	32	0	0
T310	6061	5	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3756	0	0
T65	6030	1	0	0
T216	84720	330	0	0
T233	77376	314	0	0
T238	9801	37	0	0
T255	18824	48	0	0
T256	9839	2	0	0
T259	19572	38	0	0
T260	18562	12	0	0
T272	80572	128	0	0
T310	6061	31	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1849	0	0
T65	6030	2	0	0
T216	84720	83	0	0
T233	77376	84	0	0
T238	9801	11	0	0
T255	18824	21	0	0
T256	9839	8	0	0
T259	19572	87	0	0
T260	18562	27	0	0
T272	80572	79	0	0
T310	6061	5	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2163	0	0
T65	6030	8	0	0
T216	84720	126	0	0
T233	77376	98	0	0
T238	9801	19	0	0
T255	18824	41	0	0
T256	9839	12	0	0
T259	19572	75	0	0
T260	18562	4	0	0
T272	80572	74	0	0
T310	6061	13	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2287	0	0
T216	84720	102	0	0
T233	77376	65	0	0
T238	9801	16	0	0
T255	18824	40	0	0
T256	9839	25	0	0
T259	19572	8	0	0
T260	18562	32	0	0
T272	80572	37	0	0
T274	75332	59	0	0
T310	6061	4	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2087	0	0
T65	6030	1	0	0
T216	84720	115	0	0
T233	77376	141	0	0
T238	9801	15	0	0
T255	18824	60	0	0
T256	9839	5	0	0
T259	19572	30	0	0
T260	18562	25	0	0
T272	80572	101	0	0
T310	6061	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3411	0	0
T65	6030	21	0	0
T216	84720	282	0	0
T233	77376	234	0	0
T238	9801	11	0	0
T255	18824	60	0	0
T259	19572	8	0	0
T260	18562	10	0	0
T272	80572	158	0	0
T274	75332	120	0	0
T310	6061	34	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2420	0	0
T65	6030	13	0	0
T216	84720	122	0	0
T233	77376	103	0	0
T238	9801	25	0	0
T255	18824	28	0	0
T256	9839	38	0	0
T259	19572	11	0	0
T260	18562	8	0	0
T272	80572	50	0	0
T310	6061	17	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2136	0	0
T216	84720	144	0	0
T233	77376	125	0	0
T238	9801	17	0	0
T255	18824	36	0	0
T256	9839	36	0	0
T259	19572	51	0	0
T260	18562	26	0	0
T272	80572	52	0	0
T274	75332	61	0	0
T310	6061	8	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1469	0	0
T65	6030	4	0	0
T216	84720	144	0	0
T233	77376	113	0	0
T238	9801	33	0	0
T255	18824	24	0	0
T256	9839	8	0	0
T259	19572	31	0	0
T260	18562	19	0	0
T272	80572	92	0	0
T310	6061	15	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2466	0	0
T65	6030	4	0	0
T216	84720	133	0	0
T233	77376	107	0	0
T238	9801	7	0	0
T255	18824	79	0	0
T256	9839	18	0	0
T259	19572	46	0	0
T260	18562	12	0	0
T272	80572	58	0	0
T310	6061	5	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2506	0	0
T65	6030	6	0	0
T216	84720	113	0	0
T233	77376	133	0	0
T238	9801	19	0	0
T255	18824	46	0	0
T256	9839	47	0	0
T259	19572	95	0	0
T260	18562	6	0	0
T272	80572	76	0	0
T310	6061	9	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2615	0	0
T65	6030	4	0	0
T216	84720	117	0	0
T233	77376	110	0	0
T238	9801	20	0	0
T255	18824	53	0	0
T256	9839	5	0	0
T259	19572	52	0	0
T260	18562	13	0	0
T272	80572	58	0	0
T310	6061	8	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2503	0	0
T216	84720	103	0	0
T233	77376	107	0	0
T238	9801	13	0	0
T255	18824	60	0	0
T256	9839	23	0	0
T259	19572	62	0	0
T260	18562	16	0	0
T272	80572	74	0	0
T274	75332	55	0	0
T310	6061	7	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2467	0	0
T65	6030	5	0	0
T216	84720	131	0	0
T233	77376	131	0	0
T238	9801	8	0	0
T255	18824	73	0	0
T256	9839	13	0	0
T259	19572	12	0	0
T260	18562	6	0	0
T272	80572	48	0	0
T310	6061	7	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3518	0	0
T65	6030	1	0	0
T216	84720	424	0	0
T233	77376	256	0	0
T238	9801	51	0	0
T255	18824	19	0	0
T256	9839	68	0	0
T259	19572	36	0	0
T260	18562	16	0	0
T272	80572	137	0	0
T310	6061	41	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3208	0	0
T65	6030	10	0	0
T216	84720	328	0	0
T233	77376	314	0	0
T238	9801	47	0	0
T255	18824	67	0	0
T256	9839	43	0	0
T259	19572	12	0	0
T260	18562	20	0	0
T272	80572	150	0	0
T310	6061	48	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2680	0	0
T65	6030	5	0	0
T216	84720	219	0	0
T233	77376	256	0	0
T238	9801	42	0	0
T255	18824	55	0	0
T256	9839	38	0	0
T259	19572	14	0	0
T260	18562	8	0	0
T272	80572	199	0	0
T310	6061	25	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3865	0	0
T65	6030	8	0	0
T216	84720	393	0	0
T233	77376	205	0	0
T238	9801	44	0	0
T255	18824	17	0	0
T256	9839	6	0	0
T259	19572	36	0	0
T260	18562	27	0	0
T272	80572	189	0	0
T310	6061	2	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3909	0	0
T65	6030	5	0	0
T216	84720	380	0	0
T233	77376	363	0	0
T238	9801	15	0	0
T255	18824	44	0	0
T256	9839	47	0	0
T259	19572	67	0	0
T260	18562	49	0	0
T272	80572	147	0	0
T310	6061	6	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3751	0	0
T65	6030	26	0	0
T216	84720	374	0	0
T233	77376	221	0	0
T238	9801	62	0	0
T255	18824	34	0	0
T256	9839	33	0	0
T259	19572	46	0	0
T260	18562	24	0	0
T272	80572	137	0	0
T310	6061	35	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3757	0	0
T65	6030	27	0	0
T216	84720	325	0	0
T233	77376	398	0	0
T238	9801	41	0	0
T255	18824	38	0	0
T256	9839	23	0	0
T259	19572	44	0	0
T260	18562	40	0	0
T272	80572	122	0	0
T310	6061	29	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	3854	0	0
T65	6030	3	0	0
T216	84720	269	0	0
T233	77376	342	0	0
T238	9801	45	0	0
T255	18824	12	0	0
T256	9839	47	0	0
T259	19572	40	0	0
T260	18562	4	0	0
T272	80572	138	0	0
T310	6061	51	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1404	0	0
T65	6030	6	0	0
T238	9801	3	0	0
T255	18824	74	0	0
T256	9839	2	0	0
T259	19572	69	0	0
T260	18562	30	0	0
T312	2847	1	0	0
T313	4905	5	0	0
T314	154155	1027	0	0
T315	9724	6	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2268	0	0
T65	6030	2	0	0
T216	84720	80	0	0
T233	77376	67	0	0
T238	9801	13	0	0
T255	18824	2	0	0
T256	9839	61	0	0
T259	19572	47	0	0
T260	18562	22	0	0
T272	80572	51	0	0
T310	6061	5	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2231	0	0
T216	84720	69	0	0
T233	77376	69	0	0
T238	9801	9	0	0
T255	18824	39	0	0
T256	9839	36	0	0
T259	19572	40	0	0
T260	18562	50	0	0
T272	80572	42	0	0
T274	75332	45	0	0
T310	6061	14	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1243	0	0
T65	6030	3	0	0
T216	84720	77	0	0
T233	77376	92	0	0
T238	9801	11	0	0
T255	18824	69	0	0
T256	9839	9	0	0
T259	19572	34	0	0
T260	18562	36	0	0
T272	80572	52	0	0
T310	6061	3	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1675	0	0
T216	84720	76	0	0
T233	77376	74	0	0
T238	9801	14	0	0
T255	18824	25	0	0
T256	9839	15	0	0
T259	19572	44	0	0
T260	18562	33	0	0
T272	80572	54	0	0
T274	75332	63	0	0
T310	6061	6	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1735	0	0
T216	84720	38	0	0
T233	77376	75	0	0
T238	9801	24	0	0
T255	18824	40	0	0
T256	9839	18	0	0
T259	19572	30	0	0
T260	18562	30	0	0
T272	80572	32	0	0
T274	75332	35	0	0
T310	6061	4	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2433	0	0
T216	84720	71	0	0
T233	77376	91	0	0
T238	9801	15	0	0
T255	18824	51	0	0
T256	9839	27	0	0
T259	19572	67	0	0
T260	18562	45	0	0
T272	80572	45	0	0
T274	75332	43	0	0
T310	6061	5	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2276	0	0
T65	6030	7	0	0
T216	84720	67	0	0
T233	77376	97	0	0
T238	9801	28	0	0
T255	18824	33	0	0
T256	9839	37	0	0
T259	19572	77	0	0
T260	18562	19	0	0
T272	80572	42	0	0
T310	6061	12	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	1679	0	0
T65	6030	8	0	0
T216	84720	67	0	0
T233	77376	70	0	0
T238	9801	8	0	0
T255	18824	62	0	0
T256	9839	16	0	0
T259	19572	19	0	0
T260	18562	7	0	0
T272	80572	40	0	0
T310	6061	9	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367720706	2189	0	0
T65	6030	2	0	0
T216	84720	100	0	0
T233	77376	93	0	0
T238	9801	6	0	0
T255	18824	32	0	0
T256	9839	16	0	0
T259	19572	30	0	0
T260	18562	18	0	0
T272	80572	47	0	0
T310	6061	8	0	0