Assertions
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Detail Report for Assertions

Assertions Uncovered:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A 00375778543000
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A 00375778543000
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A 00375778543000
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A 00375778543000
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A 00375778543000
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A 00375778543000
tb.dut.FpvSecCmRdReqFifoRptrCheck_A 00375778543000
tb.dut.FpvSecCmRdReqFifoWptrCheck_A 00375778543000
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A 00375778543000
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A 00375778543000
tb.dut.PrimRspPayLoad_A 00375778543000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A 00375778543000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M 00375778543000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A 00375778543001033
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A 00375778543000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M 00375778543000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 00375778543001033
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00375778543001033
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00375778543001033
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00375778543001033
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00375778543001033
tb.dut.u_prog_tl_gate.OutStandingOvfl_A 00375778543000
tb.dut.u_tl_gate.OutStandingOvfl_A 00375778543000
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty 00375778543000
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull 00375778543000
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A 00375778543000
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00375778543000
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A 00375778543000
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00375778543000

Assertions Success:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.FifoDepthCheck_A 001038103800
tb.dut.FlashAddrKnown_A 0037577854327252935600
tb.dut.FlashAddrKnown_AKnownEnable 0037577854337494997100
tb.dut.FlashKnownO_A 0037577854337494997100
tb.dut.FlashProgKnown_A 0037577854316324205800
tb.dut.FlashProgKnown_AKnownEnable 0037577854337494997100
tb.dut.FpvSecCmAddrCntAlertCheck_A 003757785435000
tb.dut.FpvSecCmArbFsmCheck_A 003757785435000
tb.dut.FpvSecCmLcCtrlFsmCheck_A 003757785435000
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A 003757785435000
tb.dut.FpvSecCmPageCntAlertCheck_A 003757785435000
tb.dut.FpvSecCmProgCnt_A 003757785435000
tb.dut.FpvSecCmRdCnt_A 003757785435000
tb.dut.FpvSecCmRdRspFifoRptrCheck_A 003757785435000
tb.dut.FpvSecCmRdRspFifoWptrCheck_A 003757785435000
tb.dut.FpvSecCmRegWeOnehotCheck_A 003757785435000
tb.dut.FpvSecCmSeedCntAlertCheck_A 003757785435000
tb.dut.FpvSecCmTlLcGateFsm_A 003757785435000
tb.dut.FpvSecCmTlProgLcGateFsm_A 003757785435000
tb.dut.FpvSecCmWipeIdx_A 003757785435000
tb.dut.FpvSecCmWordCntAlertCheck_A 003757785435000
tb.dut.IntrErrO_A 0037577854337494997100
tb.dut.IntrOpDoneKnownO_A 0037577854337494997100
tb.dut.IntrProgEmptyKnownO_A 0037577854337494997100
tb.dut.IntrProgLvlKnownO_A 0037577854337494997100
tb.dut.IntrProgRdFullKnownO_A 0037577854337494997100
tb.dut.IntrRdLvlKnownO_A 0037577854337494997100
tb.dut.MemRspPayLoad_A 00375778543461649200
tb.dut.MemRspPayLoad_AKnownEnable 0037577854337494997100
tb.dut.MemTlAReadyKnownO_A 0037577854337494997100
tb.dut.MemTlDValidKnownO_A 0037577854337494997100
tb.dut.PrimRspPayLoad_AKnownEnable 0037577854337494997100
tb.dut.PrimTlAReadyKnownO_A 0037577854337494997100
tb.dut.PrimTlDValidKnownO_A 0037577854337494997100
tb.dut.RspPayLoad_A 003755729044001753700
tb.dut.RspPayLoad_AKnownEnable 0037577854337494997100
tb.dut.TdoEnIsOne_A 0037577854337494997100
tb.dut.TdoKnown_A 0037577854337494997100
tb.dut.TlAReadyKnownO_A 0037577854337494997100
tb.dut.TlDValidKnownO_A 0037577854337494997100
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A 00378523581395300
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A 00378523581185300
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A 00378523581269000
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A 00378523581224100
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A 00378523581261100
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A 00378523581277500
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A 00378523581253700
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A 00378523581214400
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A 00378523581269000
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A 00378523581198300
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A 00378523581273100
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A 00378523581207300
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A 00378523581201400
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A 00378523581184000
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A 00378523581188000
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A 00378523581199400
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A 0037852358182500
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A 00378523581190300
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A 00378523581207200
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A 0037852358177600
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A 0037852358183800
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A 00378523581177000
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A 00378523581189300
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A 00378523581177500
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A 00378523581267800
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A 00378523581207700
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A 00378523581142600
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A 00378523581183200
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A 00378523581250600
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A 00378523581263200
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A 00378523581214500
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A 00378523581260200
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A 00378523581263500
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A 00378523581274400
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A 00378523581256700
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A 00378523581214000
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A 00378523581261200
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A 00378523581255800
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A 00378523581184400
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A 00378523581140100
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A 00378523581177100
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A 00378523581189500
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A 00378523581187600
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A 00378523581185400
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A 00378523581182300
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A 00378523581137800
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A 00378523581131000
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A 00378523581151400
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A 00378523581257600
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A 00378523581182500
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A 00378523581266700
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A 00378523581260900
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A 00378523581179400
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A 00378523581140500
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A 00378523581156000
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A 00378523581207400
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A 00378523581182900
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A 00378523581213700
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A 00378523581196800
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A 00378523581148500
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A 00378523581268600
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A 00378523581155800
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A 00378523581153000
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A 00378523581209100
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A 00378523581215100
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A 00378523581198400
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A 00378523581194500
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A 00378523581163600
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A 00378523581148200
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A 00378523581263700
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A 00378523581263800
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A 00378523581216200
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A 00378523581260300
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A 00378523581163400
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A 00378523581221600
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A 00378523581257800
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A 00378523581270200
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A 00378523581106200
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A 00378523581133000
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A 00378523581139000
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A 00378523581139400
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A 00378523581138900
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A 00378523581150900
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A 00378523581146400
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A 00378523581184500
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A 00378523581135600
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A 00378523581192900
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A 003757785435000
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A 003757785435000
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A 003757785435000
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A 003757785435000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A 003757785435000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A 003757785435000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A 003757785435000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A 003757785435000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A 003757785435000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A 003757785435000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A 003757785435000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A 003757785435000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A 003757785435000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A 003757785435000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A 003757785435000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A 003757785435000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A 003757785435000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A 003757785435000
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 003757785432000
tb.dut.tlul_assert_device.aKnown_A 003785235433536003200
tb.dut.tlul_assert_device.aKnown_AKnownEnable 0037852354337761450700
tb.dut.tlul_assert_device.aReadyKnown_A 0037852354337761450700
tb.dut.tlul_assert_device.dKnown_A 003785235434072894900
tb.dut.tlul_assert_device.dKnown_AKnownEnable 0037852354337761450700
tb.dut.tlul_assert_device.dReadyKnown_A 0037852354337761450700
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A 001248124800
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tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A 001248124800
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A 001248124800
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1020010
Category 01020010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1020010
Severity 01020010


Summary for Assertions
NUMBERPERCENT
Total Number1020100.00
Uncovered292.84
Success99197.16
Failure00.00
Incomplete151.47
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%