Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	319006	1		T1	2		T2	1		T3	2
all_values[1]	319006	1		T1	2		T2	1		T3	2
all_values[2]	319006	1		T1	2		T2	1		T3	2
all_values[3]	319006	1		T1	2		T2	1		T3	2
all_values[4]	319006	1		T1	2		T2	1		T3	2
all_values[5]	319006	1		T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	644248	1		T1	12		T2	6		T3	12
auto[1]	1269788	1		T6	14080		T7	2812		T30	13848

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	939626	1		T1	7		T2	4		T3	7
auto[1]	974410	1		T1	5		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	318845	1		T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	161	1		T249	4		T250	1		T251	2
all_values[1]	auto[0]	auto[1]	318869	1		T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	137	1		T249	5		T250	3		T251	1
all_values[2]	auto[0]	auto[0]	1560	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	52	1		T249	1		T251	2		T308	3
all_values[2]	auto[1]	auto[0]	317342	1		T6	3520		T7	703		T30	3462
all_values[2]	auto[1]	auto[1]	52	1		T250	2		T309	1		T310	1
all_values[3]	auto[0]	auto[0]	1580	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	56	1		T250	2		T251	1		T308	2
all_values[3]	auto[1]	auto[0]	89057	1		T6	1760		T7	310		T30	1731
all_values[3]	auto[1]	auto[1]	228313	1		T6	1760		T7	393		T30	1731
all_values[4]	auto[0]	auto[0]	1127	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	519	1		T1	1		T3	1		T5	1
all_values[4]	auto[1]	auto[0]	210164	1		T6	1760		T7	310		T30	1731
all_values[4]	auto[1]	auto[1]	107196	1		T6	1760		T7	393		T30	1731
all_values[5]	auto[0]	auto[0]	1496	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	144	1		T32	5		T33	1		T48	1
all_values[5]	auto[1]	auto[0]	317300	1		T6	3520		T7	703		T30	3462
all_values[5]	auto[1]	auto[1]	66	1		T249	2		T250	1		T251	3