Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	235952	1		T1	4		T2	49		T4	1336
auto[FlashEraseBank]	262425	1		T2	15		T3	1		T5	1197

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	252082	1		T1	2		T2	27		T4	678
auto[FlashOpProgram]	226882	1		T1	1		T2	25		T3	1
auto[FlashOpErase]	15413	1		T1	1		T2	12		T4	329
auto[FlashOpInvalid]	4000	1		T197	200		T198	200		T122	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	252082	1		T1	2		T2	27		T4	678
op[FlashOpProgram]	226882	1		T1	1		T2	25		T3	1
op[FlashOpErase]	15413	1		T1	1		T2	12		T4	329
read_erase_read	546	1		T5	8		T52	1		T28	2
read_prog_read	790	1		T2	7		T5	3		T52	12

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	360738	1		T1	4		T2	64		T3	1
auto[FlashPartInfo]	134282	1		T4	1336		T5	1197		T59	209
auto[FlashPartInfo1]	853	1		T8	1		T33	1		T39	1
auto[FlashPartInfo2]	2504	1		T59	2		T7	60		T21	2

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	183538	1		T1	2		T2	27		T5	34
auto[FlashPartData]	auto[FlashOpProgram]	169673	1		T1	1		T2	25		T3	1
auto[FlashPartData]	auto[FlashOpErase]	3611	1		T1	1		T2	12		T5	42
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T197	200		T198	198		T122	194
auto[FlashPartInfo]	auto[FlashOpRead]	66248	1		T4	678		T5	576		T43	735
auto[FlashPartInfo]	auto[FlashOpProgram]	56189	1		T4	329		T5	608		T59	209
auto[FlashPartInfo]	auto[FlashOpErase]	11773	1		T4	329		T5	13		T43	370
auto[FlashPartInfo]	auto[FlashOpInvalid]	72	1		T198	2		T122	4		T391	6
auto[FlashPartInfo1]	auto[FlashOpRead]	679	1		T8	1		T33	1		T39	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T122	1		T125	1		T139	32
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T122	1		T140	1		T392	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T122	2		T140	2		T392	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1617	1		T7	60		T21	2		T8	5
auto[FlashPartInfo2]	auto[FlashOpProgram]	856	1		T59	2		T8	1		T62	7
auto[FlashPartInfo2]	auto[FlashOpErase]	25	1		T129	2		T133	2		T109	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T140	2		T392	2		T393	2