Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30510	1		T1	4		T2	8		T4	660
auto[1]	54	1		T129	11		T327	1		T328	6
auto[2]	71	1		T175	8		T129	1		T176	12
auto[3]	294	1		T23	1		T128	1		T129	16

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7739	1		T1	1		T2	2		T4	165
evic_idx[1]	7742	1		T1	1		T2	2		T4	165
evic_idx[2]	7723	1		T1	1		T2	2		T4	165
evic_idx[3]	7725	1		T1	1		T2	2		T4	165

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29886	1		T1	4		T4	660		T43	732
evic_op[2]	365	1		T54	20		T23	1		T117	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7389	1		T1	1		T4	165		T43	183
evic_idx[0]	evic_op[1]	auto[1]	9	1		T129	2		T328	2		T329	1
evic_idx[0]	evic_op[1]	auto[2]	10	1		T330	3		T331	4		T196	1
evic_idx[0]	evic_op[1]	auto[3]	72	1		T129	5		T332	1		T328	2
evic_idx[0]	evic_op[2]	auto[0]	73	1		T54	5		T117	1		T183	1
evic_idx[0]	evic_op[2]	auto[1]	7	1		T74	1		T81	1		T75	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T333	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	8	1		T36	1		T195	1		T300	1
evic_idx[1]	evic_op[1]	auto[0]	7394	1		T1	1		T4	165		T43	183
evic_idx[1]	evic_op[1]	auto[1]	10	1		T129	2		T328	2		T329	1
evic_idx[1]	evic_op[1]	auto[2]	9	1		T129	1		T328	1		T330	2
evic_idx[1]	evic_op[1]	auto[3]	64	1		T129	4		T332	1		T328	2
evic_idx[1]	evic_op[2]	auto[0]	77	1		T54	5		T117	1		T183	1
evic_idx[1]	evic_op[2]	auto[1]	1	1		T74	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	17	1		T23	1		T128	1		T334	1
evic_idx[2]	evic_op[1]	auto[0]	7390	1		T1	1		T4	165		T43	183
evic_idx[2]	evic_op[1]	auto[1]	9	1		T129	4		T328	1		T330	2
evic_idx[2]	evic_op[1]	auto[2]	7	1		T328	1		T330	2		T331	2
evic_idx[2]	evic_op[1]	auto[3]	58	1		T129	3		T332	1		T328	2
evic_idx[2]	evic_op[2]	auto[0]	73	1		T54	5		T117	1		T183	1
evic_idx[2]	evic_op[2]	auto[1]	2	1		T74	1		T335	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	2	1		T295	1		T336	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	12	1		T286	1		T337	1		T338	1
evic_idx[3]	evic_op[1]	auto[0]	7392	1		T1	1		T4	165		T43	183
evic_idx[3]	evic_op[1]	auto[1]	11	1		T129	3		T328	1		T329	2
evic_idx[3]	evic_op[1]	auto[2]	8	1		T328	1		T330	1		T331	3
evic_idx[3]	evic_op[1]	auto[3]	54	1		T129	4		T332	1		T328	3
evic_idx[3]	evic_op[2]	auto[0]	76	1		T54	5		T117	1		T183	1
evic_idx[3]	evic_op[2]	auto[1]	5	1		T327	1		T74	1		T339	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T286	1		T340	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	9	1		T341	1		T342	1		T343	1